SemiSerious

Our preliminary analysis of the IM Flash Technologies’ 50nm 4Gb SLC NAND Flash unequivocally proves that it is, indeed, a 50nm device.  This moves IMFT to the head of the class in terms of the smallest process lithography.  Traditionally, it has been Samsung that has always pushed the process envelope, realizing 4Gb 65nm SLC NAND Flash in the first half of 2006.  Conventional wisdom was that this SLC-based strategy, and the corresponding process shrink, was starting to run out of steam.  However, IMFT has demonstrated that this is not necessarily the case with their 50nm solution.

This chip is quite an achievement for several reasons.  To start, this is the first actual device that our analysts have seen from the IMFT joint venture – a clear demonstration that this partnership is getting results.  Second, according to the 2005 ITRS Roadmap, the Flash Uncontacted Poly Si ½ Pitch (nm) should not be reaching 50nm until 2008.  This puts IMFT two years ahead of the ITRS schedule!

EETimes picked up details from our press release and put out an article titled “Intel, Micron trail Toshiba in flash density, says analyst”, which focused on the single level cell (SLC) and multi level cell (MLC) debate.  The article concentrated on the Mb/mm² comparison of the IMFT and Toshiba’s 8Gb 70nm MLC NAND Flash devices.  However, this is a bit like comparing apples and oranges, similar to a direct NAND and NOR comparison.  They are different implementations that accomplish the same end from an applications perspective.  If there is a solution with the required density that meets a company’s needs in terms of cost, performance, reliability, and size, then it is selected, whether it is a direct competitor or not.

The advantage of the IMFT solution is cost.  With a die size nearly 50% smaller than Toshiba’s, IMFT can produce about 50% more die per wafer.  The advantage of Toshiba is density.  By offering an 8Gb single die device, Toshiba can offer solutions for the increasing density demand of mobile consumer products.

Can IMFT continue to aggressively shrink the process lithography, enabling them to, in the near term at least, outpace competitors, even if they continue to use SLC technology while others migrate, or continue to produce, MLC?

Recently, copper appeared in the news as a replacement for traditional gold bonding wires due to the rising price of gold. War and upheaval has a way of attracting investors to gold. Looking at the 30-year history of gold prices, there are spikes in 1979 when the Soviet Red Army invaded Afghanistan as well as in 1982 during the Falkland Islands War. More recently, gold was the only winner following the US invasion of Iraq in 2003.

For obvious reasons, gold has always been viewed as an expensive commodity. Therefore, there were several groups working on more cost-effective alternatives such as copper dating back 30 or more years. Several issues have held copper back. Foremost among these is copper’s tendency to continuously form an oxide. Gold, after all, is the most inert metal there is. To achieve acceptable yields in the bonding, assembly would likely need to move to much cleaner environments than those used for gold today.

No doubt, there are many good engineers out there who could overcome the shortcomings of copper as a wirebond material. Ironically, it is probably cost-effectiveness that will stop it. Gold is more expensive, but it benefits from a 40+ year history on the job. It would take an unprecedented level of extremely costly retooling to get copper into the mainstream. It is hard to imagine even a copper wirebond tool maker getting a machine into production, let alone widespread adoption by assembly houses. Gold will not be displaced by copper, at least not for wires.

What will change in the industry is the decision point for moving a design from wirebond to flipchip. Typically today, flip-chip is not considered to be a viable option below about 200 pins. If gold continues the trend to be a more significant portion of the manufacturing cost, we will see lower I/O count devices avoiding the wirebond route. In this case, copper pillar technology might be used to lower the overall cost of the chip. Solder bumping devices that use copper back-end metallization on the IC require some special additional metals - under-bump metals or UBM - to ensure low resistance die-to-package connection. Therefore, copper pillar technology such as used in the Intel 65nm D 920 Dual Core MPU, might squeeze out the solder bumps usually used today. So copper may still have a future as a cost-saving measure in the packaging industry. 

The crisis in Lebanon seems to have subsided for now, but either way, there is an impact on the markets. The news from Wall Street this time seemed to be that investors have become more hardened to the idea of major crises. This left the Dow Jones relatively stable, and gold prices actually declined slightly.

It’s doubtful that the price of gold represents the end of the world as we know it, and it’s up to you whether you buy or “share” the REM song of that name. But that brings up the whole issue of digital rights management which will have to wait for another day.

Once promised as the replacement to conventional non-volatile memory, the prospects around MRAM are no longer as clear. Only two vendors have succeeded in bringing MRAM parts to the mass market - Cypress and Freescale. That said, Cypress discontinued their offering shortly after release and Freescale, which announced MRAM back when they were still known as Motorola, just realized commercial production of a 4M magenetoresistive memory. It’s interesting to see the Motorola symbol used on the final production device. Maybe this chip has been sitting in a warehouse for the last two years. The  Freescale 4M MR2A16A MRAM was allegedly sampling since early in 2004 after all. MRAM densities and yields remain low and it’s questionable whether this technology can make up for lost ground.

Catching up is the difficulty faced by every new generation of “flash replacement.” It seems like I have heard the end of flash technology decried throughout my career in semiconductors. Progress in our industry depends a lot on consensus as seen in predications like the International Technology Roadmap for Semiconductors maintained by the SIA. Their position is that none of the currently known NVM technologies have any longer life in terms of scalability than flash. SI’s in depth analyses of the Freescale MRAM device provides insight into the prospects for MRAM and future evolution of the memory market.

When all the world was buzzing with the promise of the new universal memory in 2004, a few predicitions proved to be accurate. Mark LaPedus at EETimes forecast MRAM as a non-event for 2005. This is a great success story for technology analysts everywhere. I wonder whether anyone predicted MRAM as a non-event for this year. I think not considering MRAM’s media shine had tarnished by late last year. Colleagues of mine at Semiconductor Insights have been studying the technology very closely for more than five years. The status of MRAM in 2001 was exhaustively examined in SI’s report An Examination of Current Developments and Future Directions of MRAM Technology. At that time, Motorola was working on magnetic tunnel junctions or MTJ. Our analysis in 2001 showed that MTJ would face significant challenges to integration with CMOS devices. Freescale thought the same thing since they switched to a magnetoresistive cell for production devices.

Let’s sum up where MRAM is today:

• MRAM will not replace DRAM because it is slower, therefore
• The “instant-on” computer is not around the corner, but
• MRAM can boot operating systems or other code faster than present-day NOR flash.

But MRAM is not going to displace Spansion or Intel flash from cell phones any time soon either. Even low-end phones have a minimum of 16M, so four of Freescale’s 4M die need to be bundled together to meet that spec. How they can catch up is anybody’s guess if you compare die efficiencies between current NOR and this Freescale MRAM. Even the single bit cell NOR flash from Intel in 90nm is over two orders of magnitude better at around 4Mbits/mm2. MRAM is that much further behind multi-bit technology which leads the industry at over 11 Mbits/mm2.

MRAM may be only middle of the pack in read time as well. The Freescale device is specified to 35ns read, while the Intel W18 series claims 11ns burst and 20ns page read times. Keep in mind that the write speed is the same, so that’s where this device shines compared to NOR. Maybe the hardest sell is in power consumption which has long been a knock on MRAM technology. The Freescale MR2A16A datasheet gives 18mA for stand-by current! Read mode current is listed at 55mA and write mode at 105mA.

But it is the high cost-per-bit that makes MRAM a non-event in the big application markets, and not necessarily the average performance or low density. In defense of Freescale’s accomplishment, it is not fair to compare a first-generation MRAM to a mature product like Flash (invented in 1984; commercially introduced in 1988). Besides, MRAM has advantages beyond speed and density such as virtually unlimited R/W cycles that makes it interesting for mission-critical applications where battery-backed-up SRAM or NV-SRAM is currently used. But that is a niche market.

The bottom line may be evolution — not revolution as Freescale’s new MRAM device seems most suited to critical military and space applications where MRAM has already been deployed at lower resolutions. MRAM is very likely to start to replace NV-SRAM since it must be cheaper to produce a more or less standard die in a standard package than to start adding batteries to the mix. DARPA at least should be happy with its early investments in Motorola and Honeywell research even if this technology doesn’t give us better cell phones or MP3 players. To really understand the how’s and why’s of Freescale’s MRAM launch, I suggest investigating one of our detailed studies of the technology.

More Information:

• Insight Report: Freescale 4M MR2A16A MRAM
• Cypress Semiconductor MRAM
• An Examination of Current Developments and Future Directions of MRAM Technology