SemiSerious

Words cannot adequately describe my excitement when I first dug into the latest edition of the ITRS and discovered that the idea of process or technology node had been eliminated. It seemed like a dream, but it was driven home when I listened to Alan Allan?s presentation at a Sematech-Semico joint event last January.

The new industry standard for specifying a number to describe an IC technology is to use a real measurement. Manufacturer marketing and industry analysts alike should now devote themselves to eliminating the dangerous and confusing “spin” that has led to so much confusion over the years. When is a “90nm process” not 90nm? What’s the difference between a 70nm and a 73nm NAND process?

For casual industry observers and corporate marketing spin-doctors, there seems to be a tendency to jump on the number with the best ring to it. This mis-information drove the SIA to take a clear stand promoting the use of unambiguous numbers and technology definitions. It makes sense. You measure a real dimension - like the wordline pitch - and translate it to the attainable mask dimension for a repetitive structure which is actually one-half of the pitch. Here is the most important part:

specify the thing you measured.

Unfortunately, the confusion continues. Doubt is cast upon numbers coming from manufacturers and analysts alike. Consider the recent example of the so-called Samsung 60nm NAND*. The product development team published the technology at the 2005 ISSCC ? ?An 8Gb Mult-Level NAND Flash Memory with 63nm STI CMOS Process Technology.?? An actual physical 60nm part makes little sense if you already have 65nm in production. Although Samsung?s press release is not using 60nm in the strict sense of a physical measurement, it does point out that the previous generation of NAND memory was 70nm ? not 65nm.

The most advanced generation of Samsung flash available is 64?1nm as measured from the wordline half-pitch. Semiconductor Insights has analyzed this memory extensively and published several reports on the findings. Semiconductor Insights believes the next stop on the Samsung flash roadmap is 55nm. Will we measure 55 exactly? I would bet against it, but we won?t be calling it 50nm.

It gets tricky when one either disputes or attempts to differentiate independent measurements or specifications that differ by only a few nanometers. Of course, this assumes a certain level of care and expertise on the part of those who publish their measurements. Alas, some analysts have made horrible blunders and produced erroneous measurements while blinded with a preconceived notion about what they would find. I will do my best to keep the numbers published here honest, accurate, and most importantly, unambiguous.

*The newest technology advancement brings 25 percent higher manufacturing productivity over the previous 70nm design technology. The newest technology advancement brings 25 percent higher manufacturing productivity over the previous 70nm design technology.?(Samsung press release, July 19, 2006)

Two semiconductor manufacturers - Intel and Micron - teamed up to create IM Flash Technologies (IMFT). This partnership is the first to reach the 50nm half-pitch generation.

This marks the first time in recent times Samsung has been surpassed in memory process technology. About 12 months ago, flash solidified its position as the new lithography driver surpassing DRAM. The first flash device to lead the way was the Samsung 70nm NAND. Samsung has occupied the lead position pushing memory technology forward for both flash and DRAM for several years. Presently, Samsung offers a 65nm product.

Samsung?s displacement as the memory technology leader by the Intel-Micron partnership was certainly a surprise. The IMFT device is well ahead in some other key flash benchmarks as well. The cell size is 0.01?m2. IMFT is the first SLC flash company to squeeze 4Gbits onto a die less than 100mm2. That puts their die density of 42Mbits/mm2 well ahead of Samsung?s high water mark of 31Mbits/mm2 for SLC NAND Flash

Besides the litho improvements to achieve a 50nm half-pitch in the wordlines, IMFT have added other process improvements:

• Innovative new STI process
• 50nm metal 1 bitline half-pitch
• Bitline and bitline contact structure reminiscent of DRAM
• Poly 3 sourceline with tungsten cladding

You can purchase a report to quickly check key dimensions at www.semiconductor.com/IMFTreports.

The Intel-Micron partnership?s technological breakthroughs are definitely a significant industry milestone. Despite surpassing Samsung?s memory technology, IMFT has not, however, become the current cost leader in flash. Toshiba still owns the top spot due to their multi-level cell (MLC) devices. The Toshiba 8G MLC density is more than one-third better than IMFT or 56Mbits/mm2.

If you want all the skinny on the skinniest technology known to man, read my colleague’s article on EETimes.