SemiSerious

To answer the question posed by Ed Keyes in EETimes, 65nm: Where are the chips?? we can now say, “TI”.

Intel was first to 65nm nearly one year ago with their MPU. Then there was UMC getting a Xilinx FPGA into production and AMD with their Opteron G processor. Now comes TI with the first 65nm baseband / applications processor for cell phones. According to TI, over 5 million units have shipped with a forecasted 10 million by the end of 2006.? The TI solution is not only the first SoC at 65nm, but also the first mobile device in this process technology. Speaking of the mobile space, 65nm Qualcomm devices have not been identified yet. Although the MSM6280 was announced as a 65nm chip, the real silicon is only a 90nm design today.

And that is news that makes TI all the more significant. The transition to 65nm production has been difficult. Until SI analyzed a TI device at 65nm, the speculation was that most processes were still somewhat immature. With the exception of Intel, who consistently drive the process curve to introduce new microprocessor generations ahead of AMD, there was only the case of UMC 65nm. With a die size of 145mm? using 65nm design rules, it?s easy to see why Xilinx needed to push the process envelope for the Virtex 5.

Intel still dominates the logic process development world to a large degree. They kept Moore?s Law on track with 65nm. But how does this compare to TI?

You could argue that both a multiprocessor unit (MPU) and a field programmable gate array (FPGA) are reasonably homogeneous designs. Intel makes a microprocessor that is a huge tangle of digital logic with an equally huge chunk of SRAM. Aside from some specialized IP cores like Rocket IO, the FPGA is huge array of repeating programmable cells with some smaller, relative to the MPU, though still extremely regular, SRAM blocks.

The baseband and applications processor, on the other hand, combines many different cores and associated memories of varying sizes into the smallest possible area. The TI 65nm chip measures only 13mm?. This is the opposite end of the chip spectrum from the 145mm? FPGA from Xilinx. While the next generation of process technology will always provide more gross die per wafer, that new process needs to net more good die per wafer than the previous process to justify the transition.” For the case of TI’s 65nm SoC, the achievement is very clear. They have produced a complex, cost-effective SoC device that required a better characterized, modelled, and more robust process.

Pictured Above: TI 65nm SRAM Cell (Diffusion Level Layout)

The Sony Playstation 3 finally arrived on store shelves in select corners of the globe this week. Sony’s complex third generation gaming console has experienced multiple delays - shipping at least a year later than hoped by Sony execs and gaming fans everywhere. After much anticipation, we finally received the Sony Playstation 3 and got to have look inside.

The Playstation 3 is Sony’s entry into the next generation of gaming consoles. Sony claims that this is the most powerful gaming system around, and has additional features that move it beyond just gaming, like the BlueRay player.

The semiconductor world has looked forward to the launch of the Cell MPU as a significant milestone in computer design for the masses. The Cell device was to be designed from the very beginning with 65nm process technology in mind. But alas, this is all hindsight. Sony had to opt for the Cell device in 90nm technology just to avoid being even further behind the year lead of the Microsoft XBox360 and soon to be released Nintendo Wii.

Stay tuned as we examine the Playstation 3 and the devices inside that make it tick.

Intel was not only the first manufacturer to produce a 65nm advanced logic process, they are also onto their third revision of the generation. Among the tweaks in the Xeon is an increase in germanium concentration. The most striking, though, is that Xeon appears to be the first ever device to use FUSI - or FUlly SIlicided - gates.

This is indeed a milestone of merit. I did not expect to see FUSI gates until 45nm, and not any widespread use until 32nm. In fact, there are people in the industry who don’t believe FUSI will work at all.

Although Intel is always the safe bet to employ new technology first, did Intel really mean to create a FUSI gate? Maybe Intel is trying to push the limits on the nickel-silicide process. The bottom line is that the FUSI on this generation of Intel seems to be a mere process variation.

The transistor performance measured did not indicate any problems on the devices we measured. But having a few devices with this much structural variation peppered through a chip as complicated as the Xeon just can?t be a good thing. For 65nm, Intel’s recipe is more like FUSILI.

Intel 65nm PFET gate virtually completely silicided by nickel

Atomic number contrast highlighting extent of nickel silicidation on Intel PFET.