SemiSerious

In the constant quest to increase the density of memory bits in each square millimeter of silicon, DRAM makers have looked up and down. First, there were storage capacitors stacked above the active devices. Then IBM developed trench technology (now widely exploited by Qimonda) to bury the capacitor deep into the substrate.

More recently, Samsung introduced a trench design, not for the capacitor, but for the cell access transistor. Samsung was already exploiting the area above the active area with stacked capacitors over the bit lines. Early last year, the Samsung processing team started a move in the other direction. The so-called Recessed Cell Array Transistor ? or RCAT ? exploited the vertical dimension into the substrate to fit a longer channel FET into the space of a more aggressively scaled device. This meant lower cell leakage and relaxed refresh cycle design.

It appears now that the concept is really catching on. The image sensor group from Samsung announced a trench transistor for its pixel transfer gate at IEDM last week. Now other companies are jumping on the bandwagon. Hynix uses an RCAT design in their 80nm 512M DDR2 DRAM that is very similar to Samsung?s original design.

Now that the RCAT is expanding its presence in the semiconductor community, the originators of the design are taking it one step further. Samsung uses a Sphere-Shaped Recessed Channel Access Transistor (S-RCAT) in their 80nm DRAM process that is? currently under the intense scrutiny of SI?s process analysis gurus. Samsung detailed this second generation trench FET as a solution for 70nm and beyond at VLSI Technology 2005, but those seeking more intimate details will have to wait for an upcoming report from SI.

The theme of this trip for me was, “I get by with a little help from my friends.” Upon arriving in San Francisco, I found myself in a taxi bound for the conference hotel without my wallet and barely enough cash for the fare. Fortunately, two of my SI process analysis colleagues were already there, and they were gracious (and trusting) enough to put my room on their own credit card. Problem solved.

As always, Sunday is a training day. Two tracks were offered, and I chose the “Memory Technologies for 45nm and beyond.” This offered some interesting material. There were excellent sections on SRAM (Harold Pilo, IBM), DRAM (Howard Kirsch, Micron), and emerging NVM (Agostino Pirovano, STMicroelectronics). In my experience, STMicro presentations at these events are always excellent. This was another thorough and objective summary of a hot topic area. Anyone getting started in understanding current and future trends for non-volatile memory should start with this presentation.

Monday morning began with presentation of the yearly Electron Device Society Awards along with three plenary talks. C.G. Hwang?s from Samsung gave an especially entertaining lecture, “New Paradigms in Silicon Industry, Business, and Technology.” How could anyone doubt that Samsung will be the industry?s number one some day after listening to this speech?

The Monday reception offers an excellent chance to meet old friends and establish new contacts in the main brain trust of the semiconductor technology. My evening was abbreviated however. It was only a quick hello to Scott Jones, our ICKnowledge partner, and a quick good-bye for me. My farewell also turned out to be quite final (in terms of the conference). My early departure from the reception on Monday night was driven by a horrible intestinal bug. I dared not leave my hotel room for the rest of the conference.

And that?s where my friends came to my aid again. Ramesh and Moira kept tabs on me the rest of the time to make sure I was still alive. Between the drugs and a half-gallon Pedialyte supplied by Moira, I was able to re-hydrate myself and establish sufficient electrolyte levels for the long flight home Wednesday night.

I hope to be a more active participant next year, but until then, I will post more summary and opinion of the technical content from this year?s IEDM. For this too, I will need a lot of help from my friends.

Macronix recently announced that phase change memory (PCM) developed jointly with IBM and Qimonda had proven its viability below 20nm. The same DigiTimes article pointed out that this PCM technology proved it could overcome the ?physical barriers? currently inhibiting production of 65nm NOR flash.

These comments are puzzling considering SI has already completed a comprehensive analysis of Intel 65nm production NOR flash. Both detailed structural analysis and characterization of the individual FET dc performance suggest that NOR flash is performing very well at 65nm. Furthermore, Intel?s 65nm floating gate NOR flash was primarily a shrink of?Intel’s 90nm ETOX IX process that required little in the way of new materials or processes.

Although my colleagues and I are quite keen on PCM, it?s too early to put floating gate flash to bed. After all, we have also exhaustively studied a production 50nm NAND technology from the Intel-Micron partnership.

Above: Intel NOR Flash with floating gate space dimension of 65nm

Reliable Plant magazine picked up an announcement that Texas Instruments had won the Semiconductor International Top Fab of the Year award. TI is the first manufacturer to make use of 65nm process technology for a low cost logic device. Considering the challenges industry-wide at 65nm, that other 65nm ships on the market are for very high-end applications, and that TI has pushed yields to a point where it could leverage the cost advantages of 65nm, this comes as no surprise. Congratulations to all TI DMOS6 staff.