SemiSerious

45 years ago, planarization of the integrated circuit was a revolution that spawned Moore’s Law. Robert Noyce’s work took the idea of the IC in a direction that arguably shaped our information age.

For the last several years, we braced for the end of Moore’s Law because planar technology would not continue to scale fast enough. The third dimension was required and various types of MuGFET (multi-gate FET) or other vertical transistor types have been widely touted as the solution. The FinFET is arguably the most famous of these.

Of course, the DRAM community became urgently aware of the third dimension many years ago as planar capacitors could no longer store enough charge to make a practical cell as bit densities increased. But active devices, the FETs that virtually all technology require, continued to be constrained to two dimensions.

Enter Samsung. For their 90nm DRAM process, Samsung introduced the first volume production device to incorporate an active device that was truly 3D. The device employs a substrate trench for the channel to squeeze a wider, longer channel transistor into the same piece of silicon real estate as a much smaller planar device. Samsung named their approach the Recessed Channel Array Transistor – or RCAT.

Samsung takes the RCAT a step further at 80nm. The mostly cylindrical trench of the 90nm generation has been augmented by a spherically-shaped ball to increase surface area of the recessed channel even further. Now they have SRCAT.

At 80nm, Samsung has included several interesting features. Using the new array transistor and a 6F2 design, Samsung creates the smallest cell on record at 0.0375µm2. It is actually the cell size that positions the 512M DDR2 as 80nm. The half-pitch of wordlines is only 85nm. The proof of this technology is really in the bit density. This 512M DRAM reaches a high watermark of 10.9Mbits/mm2 at 80nm.

Samsung employs interesting new materials to augment the S-RCAT and other scaling tricks. For the first time, germanium appears in a commercial memory. The cell plate polysilicon is Poly-Si1-xGex. Incorporating germanium improves the conductivity of the cell plate and also reduces the thermal budget requirement of the process. The capacitor dielectric is an advanced high-K stack. As part of what appears to be a corporate campaign to re-brand everything, Samsung refers to this dielectric as AfO. Really, this is a mix of aluminum oxide and hafnium oxide. Purists might prefer AlHfO.

As a few devices start to blaze an FET trail into the third dimension, many more announcements will continue to appear. There is one very interesting and noteworthy exception to this: flash memory. Check back soon for an in-depth review of new technologies for flash scaling.