SemiSerious

After relatively quietly becoming the dominant force in image sensors in the short span of three years, Micron is beginning to show more signs of becoming an Intel-like force in the industry.

The most obvious example of this was the Patent Power article in the November 2006 IEEE Spectrum. 1790 Analytics conducted the first ever patent survey for Spectrum. Micron was ranked as the overall top patenting company just ahead of traditional powerhouse IBM. The survey looked at more than simple numbers of patents granted in order to judge the strength of the portfolio.

Speaking of that patent power, I don’t doubt that a large part of Micron Imaging’s success can be attributed to the intellectual property they acquired through the purchase of Photbit. Photobit was a spinoff of Jet Propulsion Labs which is considered by many to be the birthplace of the CMOS active pixel image sensor. The marriage of imager and manufacturing know-how certainly spawned the success of the imaging business at Micron.

Micron recently moved to build upon the imaging division’s success with the acquisition of another company with a lot of industry-leading expertise in the field - Avago. The Avago purchase also adds another big pile of quality patents in the field given their lineage and the years of prolific patent filings at Hewlett-Packard. (HP is ranked third in the Spectrum list, nowadays, though, only under systems and software.)

I think the connection between Micron and Intel goes beyond their joint venture for NAND flash. Micron is starting to sound a bit like the chip giant in the news. On Friday, Semicondutor International ran an article about Micron’s recent ribbon-cutting at a materials testing lab at UW. Micron launched this research facility with around $1M of cash and equipment. The goal of the lab is more fundamental and forward-thinking than you might expect from a manufacturer of commodity devices like image sensors and DRAM. The mandate is to study “combinatorial” materials for possible silicon replacements. This is intended to go beyond the only such material to make it into large scale CMOS production so far - SiGe.

In one of three plenary talks given at the 2006 International Electron Devices Meeting (IEDM), Dr. Chang-Gyu Hwang, president and CEO of Samsung Electronics’ Semiconductor Business, suggested that we are about to experience the largest semiconductor industry transition ever. Chip Shots and Physorg have more detailed accounts of this talk.

An entertaining Dr. Hwang predicted, “The approaching era of electronics technology advancement – the Fusion Era – will be massive in scope, encompassing the fields of information technology (IT), bio-technology (BT), and nano-technology (NT) and will create boundless opportunities for new growth to the semiconductor industry.” Dr. Hwang believes this long period of new growth will begin around 2010.

Bio-tech, health care, robotics, aerospace, solar cell, and environment-friendly R&D fields are expected to combine in critical ways to herald the dawning of the “New Era of Fusion Technology.” Semiconductor advancements will play a pivotal role in enabling this new trend, Dr. Hwang said.

“Unlike the paradigm shift from the personal computer to mobile and digital consumer applications, the introduction of massive-scale fusion technology – which represents the organic convergence of IT, BT and NT, will bring together a wide range of technology-related professions as the foundation for a new technology frontier,” Dr. Hwang said. “This historic new frontier will change the way we develop and harness semiconductor technologies in substantially improving the level of day-to-day convenience for consumers.”

“Commencement of the Fusion Era depends on the successful development of high-density, ultra-small, multi-featured semiconductor chips and multi-faceted, cross-industry solutions. To enter the new era, Dr. Hwang said it is essential to first overcome today’s limits in nano-technology.” You can see the rest of the SEC press release here.

It all sounds quite grand. Perhaps not for the company that set its sights on displacing Intel as the largest semi manufacturer. To-date at Samsung, the “Fusion” era belongs to memory. Once again, this should come as no surprise since Samsung has long dominated both DRAM and flash. But what does it have to do with multi-featured chips and cross-industry solutions?

Samsung’s first fusing exercise was the OneNAND. Not planning to be outdone, the phase-change memory unit shrunk the acronym from PCRAM to PRAM. Obviously, the explanation of PRAM from the corporation planning to dominate the industry was “Perfect RAM.”

The latest fusion device from Samsung is OneDRAM. As you might expect, this new device offers “better performance, with faster speed and lower power consumption and a lower chip count, with reduced area coverage on the printed circuit board.”

Taking nothing away from the technological achievements of the Samsung memories, it seems the One devices are more high density devices leveraging low cost processing to nibble at the edges of applications more typically using special-purpose memory.

Perhaps the DaVinci Code and the legend of the Priory of Sion is no longer topical, but Sion’s namesake compound – SiON or silicon oxynitride – is extremely relevant in the semiconductor industry. Unlike Sion though, SiON at 65nm is no hoax – pushing exotic high-K materials out to 45nm for high performance logic processes and possibly further.

When Intel was pre-occupied with clock speed and the gigahertz race, their fabs pushed gate dielectrics very hard. Unfortunately, leakage through those ever-thinner dielectrics sucked a lot of power even when the logic gates were idle. Power consumption concerns brought an end to thinning the gate dielectric at 90nm for Intel. Their 65nm process uses the same physical dimension of 1.2nm.  The strategy for the entire industry to increase transistor performance for the 65nm generation is to optimize the nitridation processes and increase the nitrogen content in the gate dielectric film. Higher nitrogen content increases the dielectric content of the film which has the same effect as a thinner film of lower K value. The effective oxide thickness or EOT allows different materials to be easily compared by referring them to the pure oxide of silicon , SiO2.

All this begs the question, “Wouldn’t it be great if you could actually look deeply into these ultra-thin films to see how much nitrogen they contain and where it is localized?”

Believe it or not, there is now a way study of state-of-the-art gate dielectrics on real world production parts.  A new report from Semiconductor Insights reveals the strategy for decreasing EOT just as the industry reacts to announcements by both Intel and the IBM alliance that their respective 45nm transistors will incorporate hafnium-based dielectrics along with metal gates. SI’s landmark new report provides details of the changes in nitrogen content through the dielectric from channel to gate. High performance AMD, Intel and UMC processes are compared along with the low stand-by power TI process.

Along with standard high resolution lattice fringe TEM imaging that provides the most accurate measurement of film thickness, electron energy loss spectroscopy or EELS data are analyzed to create an understanding of the nitridation process and its effect on device performance.

Hafnium-based dielectric films promise a lot and offer a great opportunity for analysis when they arrive later next year. Fortunately, the technology needed to study those devices is available now. For now, there is a lot to learn from the optimized SiON films at 65nm. But if you just must know more about hafnium oxide high-K in production, Samsung uses it in their 80nm DRAM capacitor.