SemiSerious

This is my second review of papers to be presented at the VLSI Technology Symposium. Today, I will take a look at the most promising papers on phase change memory technology (PCM or PRAM). Today at its spring development forum in Beijing, Intel announced that it will produce a 128M 90nm PRAM later this year. This is bound to create some extra buzz around the many good PRAM papers to look forward to at VLSI.

Samsung dominates the PRAM submissions as you might expect from some of their announcements in the past year. They will present a phase change cell based on GeSbTe for sub-50nm generations that appears to keep reset current below 260µA.  PRAM designs typically suffer from high currents required to heat and change the phase of the active layers. In another paper, Samsung memory engineers plan to present a novel heat dissipating cell scheme to improve the reset characteristics across a large (512M) array.

Naturally, Intel does have a paper in the NVM category. Oddly, though, it is a traditional floating gate NOR. Intel’s flash team will present “A Scalable Self-Aligned Contact NOR Flash Technology.” Sounds a bit bland, but it promises technology for 40nm and beyond. At 65nm, the cell area is only 0.036 square microns which is a cell area factor improvement from 10.6 on their 65nm production technology down to 8.5. This team’s ability to push the floating gate NOR cell is somewhat at odds to the PRAM announcement that was billed - in the EETimes article anyway - as the replacement for the floating gate.

In a way, it makes sense for Intel to get PRAM into the market first. But you need to look back a few years before STMicroelectronics began to make big strides and invest a lot of energy in PRAM development. Intel was the first major player to invest in phase change memory by funding a spin-off from the creators of ovonics. Energy Conversion Devices was the corporate entity that grew out of the pioneering work of Stanford R. Ovshinsky in 1960. A separate company - Ovonyx - was formed in 1999 to commercialize the “Ovonic Unified Memory” or OUM. Today, OUM has a sexier name. PRAM is “perfect RAM” in the Samsung vernacular.

That’s enough of a history lesson though. It does sound as though we will have a chance for the Intel PRAM and NOR flash to go “head-to-head” soon albeit with PRAM making its mark using older generation litho tools.

Despite the talk of Intel mass production with Samsung and STMicro doubtless charging hard, an IBM paper may have the most interesting new technology to present. Details are sketchy to non-existent at this point regarding, “Novel Lithography-Independent Pore Phase change Memory.” It certainly sounds like the first NVM session will be worth attending to hear about this work along with Samsung’s.

TSMC recently announced it would put its 45nm technology into production this coming September. For me, this begs the question, “What’s changed?” After all, TSMC was relatively late to the 65nm party. Consider the following:

• 65nm was generally a shrink of 90nm
• 45nm will be “new”
• TSMC followed most of the major IDMs and rival UMC into 65nm production
• The most prolific large, commodity IC’s - NVidia and AMD (ATi) graphics chips - are just presently transitioning to the 80nm half-node
• TSMC will continue the half-node strategy with a shrink from 65nm down to 55nm

Given these factors, what 45nm devices can we expect to be getting into products in Q4? Will it be handheld chipsets as speculated at Beyond3D? For more information regarding a real process - 65nm - I would recommend reading the rest of the news at Beyond 3D for some very good analysis of which GPU’s to expect and when.

TSMC has revealed an overview of what its 45nm technology will include:

• 193nm immersion photolithography
• Extreme low-k (ELK) material (for the inter-level dielectrics I hope!)
• “Exceptionally high” gate density and high-density 6T SRAM

TSMC does an excellent job of SRAM cell scaling for its SoC customers.  Looking at today’s 65nm 6T SRAM from TSMC, the cell area factor is 123 or 0.52 square microns which is very close to the minimum theoretical size. Based on this, I expect the 45nm 6T SRAM cell size to be around 0.25 square microns. (The most aggressive SRAM scaling has been from TI for several recent generations. Their 65nm 6T cell is only 0.48 square microns.)

…as well as some notable exclusions:

• Metal gates
• High-K gate dielectric.

 According to the announcement, TSMC’s Low Power (LP) 45nm process is expected to be available first, followed soon after by the General Purpose and High Performance (GS) process. Does this seem strange? Given that TSMC will avoid high-K gate dielectric materials until 32nm, I would expect that the low power processes demand more tweaking. However, this announcement does not mention any Low Standby Power (LSTP) process which is the driver for reducing gate leakage and off current. So if it’s true that the LP version will appear first, the 45nm platform development is being driven by the hot market and trying to grab as much of it as possible to attract big outsourced wafer starts from IDM’s like TI.

Once again last week, the organizers of the VLSI Technology and Circuit Symposia organizers supplied me with this year’s abstracts and conference summary. As always, there are a lot of great papers with all geographic regions well-represented. For today’s blog, I will start a series of posts about which papers and technologies to watch for June 12 to 14 in Kyoto.

45nm and high-K metal gate have been the hot topics ever since Intel and IBM announced them for their respective high performance CMOS logic platforms, so I will start with 45nm logic today. There are many interesting papers planned for VLSI Tech related to technologies for 45nm logic. IBM and IMEC are the best represented organizations. There are no Intel logic papers at all. You can find out about Intel 45nm from a platform perspective with some awesome videos from Scoble at PodTechNews. This video is the edited celebration of Intel’s success driving Moore’s Law. You can also get the “fab” tour from Mark Bohr, the device testing lab, Kaizad Mistry in the bunny suit, and the whole 45nm MPU line-up. Back to VLSI, there are a smattering of contributions from AMD, Fujitsu, NEC, Renesas and Toshiba as well.

The highlight session will feature one IBM presentation that is bound to generate interest. “High Performance Transistors Featured in an Aggressively Scaled 45nm Bulk CMOS technology” describes an allegedly world-leading drive current performance of 1150µA/µm for NFET and 785µA/µm for PFET. Just as an aside, I should point out that a Samsung paper promises 1620µA/µm for NFET. It is interesting to me that IBM is describing a bulk rather than SOI technology for 45nm. IBM has produced SOI IC’s at both 130 and 90nm. The interconnect scheme features ultra low-K of 2.4. The gate material is not mentioned.

In fact, there are no IBM papers that mention the gate material. Many other presenters will, however. That list includes IMEC, National university of Singapore, and Samsung. The commonality among these is that they will all discuss various flavors of FUSI or fully-silicided poly as opposed to metal gate structures. It would appear that the FUSI concept is not only alive and well but has a large following in the industry.