TSMC 45nm ready in September – what’s changed?
TSMC recently announced it would put its 45nm technology into production this coming September. For me, this begs the question, “What’s changed?” After all, TSMC was relatively late to the 65nm party. Consider the following:
- 65nm was generally a shrink of 90nm
- 45nm will be “new”
- TSMC followed most of the major IDMs and rival UMC into 65nm production
- The most prolific large, commodity IC’s – NVidia and AMD (ATi) graphics chips – are just presently transitioning to the 80nm half-node
- TSMC will continue the half-node strategy with a shrink from 65nm down to 55nm
Given these factors, what 45nm devices can we expect to be getting into products in Q4? Will it be handheld chipsets as speculated at Beyond3D? For more information regarding a real process – 65nm – I would recommend reading the rest of the news at Beyond 3D for some very good analysis of which GPU’s to expect and when.
TSMC has revealed an overview of what its 45nm technology will include:
- 193nm immersion photolithography
- Extreme low-k (ELK) material (for the inter-level dielectrics I hope!)
- “Exceptionally high” gate density and high-density 6T SRAM
TSMC does an excellent job of SRAM cell scaling for its SoC customers. 
Looking at today’s 65nm 6T SRAM from TSMC, the cell area factor is 123 or 0.52 square microns which is very close to the minimum theoretical size. Based on this, I expect the 45nm 6T SRAM cell size to be around 0.25 square microns. (The most aggressive SRAM scaling has been from TI for several recent generations. Their 65nm 6T cell is only 0.48 square microns.)
…as well as some notable exclusions:
- Metal gates
- High-K gate dielectric.
According to the announcement, TSMC’s Low Power (LP) 45nm process is expected to be available first, followed soon after by the General Purpose and High Performance (GS) process. Does this seem strange? Given that TSMC will avoid high-K gate dielectric materials until 32nm, I would expect that the low power processes demand more tweaking. However, this announcement does not mention any Low Standby Power (LSTP) process which is the driver for reducing gate leakage and off current. So if it’s true that the LP version will appear first, the 45nm platform development is being driven by the hot market and trying to grab as much of it as possible to attract big outsourced wafer starts from IDM’s like TI.