Archive for June, 2007

We’ve Got the Power

Dark Field TEM of GaAs pHEMT

Trying to mute the old joke that compound semiconductors are the technology of the future and always will be, Dr. Vu Ho recently attended the 2007 International Conference on Compound Semiconductor Manufacturing Technology. The III-V compounds and related materials such as GaAs, GaN and InP have for years been a mainstay of advanced platforms in military and aerospace applications. However, they have not penetrated deeply into the high volume consumer segment that gets executives and investors salivating.

The higher performance offered by the “un-silicon” materials have been well known for many years. Higher carrier mobilities and semi-insulating substrates enable transistors and circuits to operate at higher frequencies and with lower losses (see more details here). For many years, the competition for maximum operating frequencies - f_T and f_MAX - put III-V’s well ahead and kept silicon devices out of the running. In the lucrative cell phone portion of the radio frequency market, compound devices established and maintained a foothold. Those components are all related to the RF front-end. Duplexer filters, switches, output power amplifiers, and receiver amplifiers (LNA’s) were all once III-V based. The first erosion of this share was still a compound, but still silicon-based, as silicon-germanium - SiGe - grabbed a piece of the power amplifier market.

Unfortunately for the III-V community, the huge momentum and power of the silicon world continued to push into this space. In the quest for becoming all-digital, today even low-power stages of the RF path are in digital CMOS. There is even an RF switch in Si - albeit on sapphire. In fact, aggressive scaling CMOS transistor dimensions has driven the speed performance to near III-V levels with all competitors reaching hundreds of gigahertz.

Despite the switching speed, transistor density, and relative ease of integrating many functions in one technology platform, CMOS may not win out. Dr. Ho points out that the breakdown voltage and power handling limitations of silicon devices (including SiGe) will limit their march to higher operating frequencies. According to Dr. Ho, the future of III-V devices looks bright.

Power up.

 

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2007 IEEE International Interconnect Technology Conference

IBM Air Gap Test ChipA couple of weeks ago, my good friend and semiconductor analysis colleague, Mark Chambers, attended the IITC in San Francisco. The sessions were held from June 4 to 6 at the Hyatt Regency at San Francisco Airport. Because the dates spanned my wedding anniversary and wife’s birthday and the conference site was far from downtown, I could not attend and Mark has promised not to engage in any “San Francisco” humour.

I talked to Mark about the IITC, and he provided me the following thoughtful and insightful comments.

DS: So Mark, do you have any comments about the conference beyond what I just read at Semiconductor International?

MC: You know how you can witness an event, spend a little time digesting it, then read an article about it and wonder if you were at the same event as the author of the article?

DS: I have the same experience if I watch an entire hockey game on TV and then see the highlights on the sports news.

MC: This article suggests that the “popular” issue of the day was 3-D integration. There were a number of interesting papers presented on the topic, including one from IBM where they mounted SRAM over an 80 core processor and made direct connection to a specific core. LETI presented, as they did last year, their scheme for 3D which uses copper “nails” which is really a variation on the through silicon via (TSV also refferred to as ISV in the article hyperlinked above), although with different processing steps.

But I don’t feel it was any more popular than other themes in the conference. In fact I would have thought there was more attention paid to the papers on low-k including the reliability issues (because there are many).

Dan Edelstein - the manager of the department that made the press release about IBM’s air gap - made a presentation that was broad in the technologies covered, but would only reveal the same info that was in the press release. A paper on IBM’s air gap will be presented at the Advanced Metallization Conference in October. Dan Edelstein will also be giving a tutorial session at that conference.

As a general comment, the papers presented this year seemed like a bit of rehash of last year, with some refinements thrown in. I sense a growing cynicism about whether we’ll see an integrated low-k in production that is less than 2.2 (obviously there is skepticism about IBM’s air/vacuum as a viable dielectric) . Overall, I was fascinated by most of the papers presented as they focused in on the practical issues of following the ITRS. I got the impression that there was no further discussion about the longevity of Moore’s Law, rather, there was a lot of imagination about what happens after its collapse. Only 2 papers on CNTs appeared this year.

DS: What was the attendance like? 

MC: I don’t have actuals but I think there were more there than last year. I’m guessing closer to 1000 which would put it at its highest attendance ever. 

DS: What type of attendees were most in evidence - students, engineers, management etc?

MC: The majority were engineering types by my guesstimates with some management and most of the posters by grad students.

DS: Were most of the attendees North American, or what guesstimate would you make of the breakdown - Asia, US, Europe?

MC: There was a strong representation from the Pacific Rim and Europe, combined probably 50%, the remainder from North America.   When I think about it China (unless you include TSMC and UMC) was conspicuously absent, at least from the list of presenters anyways. 

DS: What was the buzz?

MC: IBM’s press release on AGE (air gap exclusion) was obviously on a lot of people’s minds due to the integrity issues associated with it, but everyone from IBM was obviously told to stay mum on the subject. I had lunch with one of the team members and couldn’t pry anything out of him (discreetly, of course).Other papers on AGE included the traditional pinch off method with CVD but there was a really interesting method presented by NXP/Dow that included the use of a thermally degradable dielectric to produce voids that, if it worked as claimed, circumvented the IBM problem with mis-aligned vias.

DS: What technology seemed to attract the most attention?

MC: Not an easy question to answer. In general the audience was unemotional (refer to earlier comments on attendance). Many papers only got questions because of the long pause waiting for questions. Wafer to wafer integration (or chip to chip) seems to be emerging as a given. One paper suggested it was no longer an innovation but rather an evolution.

DS: What sessions did you attend?

MC: All presentations were in series. I went to all of them.

DS: Good answer in case your manager reads this. Which was the most interesting session?

MC: I’m fascinated by the idea of AGE. It’s interesting to watch the various approaches taken to its integration - nothing has been presented that includes data on reliability after CMP or packaging. Throw 3D on top of that (literally) and it will be interesting to see if it makes it to production. There were only 3 papers on it this year and IBM seems to be the furthest along in development (at least, according to the press). I’m aware that AGE is an old technology in some ways but so much has changed since it’s inclusion in devices from years ago. The thermally degrading dielectric looks interesting. 

Dan Edelstein made the IBM presentation that touched on AGE and was quite communicative (except with reference to AGE).

DS: What seemed to be the most popular session?

MC: I don’t recall a most popular.

DS: Hmmm… Okay, so what papers attracted the most questions?

MC: When Dan Edelstein presented his paper on advanced Cu metallization, he was able to stickhandle like Sid the Kid (DS - if you don’t get the hockey reference please link here) to avoid those referring to AGE. There were lots of questions on the thermally degrading dielectric as well.

DS: Which companies attendees seemed to be asking the most questions? 

MC: There were 3 people who were consistently asking questions, and the cynic in me thought that it was merely an attempt to get air time for themselves or their company.

DS: What technology was the hottest in terms of the number of papers?

MC: At a first glance, I would say that there were roughly an equal number of presentations surrounding 3 topics:

  • lowering k in dielectrics,
  • decreasing R in the metal lines and the last,
  • how the first two affect reliability

DS: What company was the most prolific at the conference?

MC: I would say it’s between IMEC, Crolles2 Alliance (STM)  and Freescale. 

DS: Mark, that was great. Thanks for your time, but most of all, thank you for your analysis. You really cut through a lot of the bull that someone attending the event might have to suffer. 

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Image Sensors and Lobster - News from IISW

SCM of CCD LayoutEasier than choosing a wine for shellfish was my decision to attend the 2007 International Image Sensor Workshop held last week in beautiful (literally - see the translation) Ogunquit, Maine. The huge lobster was served up with an even bigger dose of the latest research in imaging technology. The workshop - formerly known as CCD and AIS - is small, but kept that way to provide an open and friendly atmosphere for the brightest minds in imaging technology. Registration was filled within two days, well before I could respond. Fortunately, our work on Scanning Capacitance Microscopy (SCM) was accepted as a poster presentation.

Three relatively new ideas appear poised to challenge the CMOS image sensor (CIS) used today everywhere from Canon professional cameras to toys. In no particular order

  • Back-side illumination (BID)
  • Active layer over IC (AIC), and
  • Single Photon Avalanche Detectors (SPAD)

have each progressed to a point where they should be taken seriously as mainstream contenders. Conceptually, each has well-known advantages over the standard (CIS) currently in production where the photosensitive element converts light into electrical charge only after the photons have traversed a thick stack required for the interconnect levels of CIS or any other IC. Standard CIS designs enjoy a big development, mass production, and (probably most importantly) market head-start. Scaling of the CIS pixel is feasible for the next two generations - 1.4 and 1µm. Beyond that, one of these newcomers will likely carry the torch.

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