SemiSerious

MIT Technology Review ran a very interesting story about printable electronics this week. Kovio, a company spun out of MIT’s Media Lab, announced a new process for printing transistors with inkjet printing techniques. According to this report, Kovio may begin production with disposable smart cards for public transit. Performance of Kovio devices will be better than what has been reported to date for IC’s created with commercial printing technology. The reason is that Kovio is the only group known to be applying this approach to inorganic materials.

Technology Review predicted several products for printed electronics including RFID tags and very large, full wall type displays. For a real potential boost to RFID adoption for inventory control, TR suggests that the cost of making an RFID tags this way could dip well below five cents.

But SI Senior Scientist, Dr. Ray Haythornthwaite, made these predicitions more than five years ago. In a report that was too early for its time or our sales force, Ray had already predicted electronic “wallpaper” that would change according to your mood or desire for instant redecorating. (Satisying my wife’s interior design whims would be so much easier if this product was available today.) The landmark, An Examination of Current Developments and Future Directions of Organic Semiconductor Technology (March 2002), provided a thorough examination of the early research into organic electronics and predicted the future for the technology. Everyone is still looking forward, but the field seems to be inching closer to making some real products.

Perhaps the killer app for ink-jet IC printing is the RFID tag. Ray also foresaw this as an obvious use for this technology. His rationale was that the packing box was there anyway, space was not (usually) at a premium. Why not just spray it on? Oddly enough, this outside-the-box thinking came at a time when our own spin-off company, Symagery Microsystems, was trying to break into the 2D barcode space. The transitioning of barcodes from 1D to 2D was evolutionary. The idea of printing a smart RFID tag to completely replace the barcode was certainly revolutionary. Ray is now retired from Semiconductor Insights but is available part-time for consulting in the semiconductor field. I don’t want to put his email here for spambots, but he is not hard to find on the web (not many Haythornthwaites in my phone book anyways).

Perhaps we can coin a new term in this nanotech era – millitech for millimeter-scale electronics. Using the ubiquitous ink-jet reverses some other trends – maybe even Moore’s Law. Millitech scaling trends and large scale integration would refer to ever-larger circuits covering more available real estate. This may put technology into the hands of ordinary people in contrast to the evermore exclusive club of megacorporations that can afford to build billion dollar wafer fabs. Consider one San Francisco artist who attempted to use nanobots as a form of high-tech graffiti, littering the little electronic insects around. Why not stick to a more traditional style of the art using spray cans? Different colors are replaced by the various transistor building materials, and voila! A new urban art form is born that can sense its audience, react and vary the imagery according to it.

Spray-on ICs – why not? Here are some links to some other, perhaps less-anticipated products offered in such a form:

http://gizmodo.com/gadgets/technology/spray-on-a-computer-133076.php

http://nexus404.com/Blog/2006/12/01/spray-condom/

http://www.cpr-savers.com/Industrials/bandas2/bandage%20spray.html

http://www.thisnext.com/item/21BD8AB8/NYC-Organic-Spray-On-Tan

http://www.uniquepaving.com.au/spray-on-paving.htm

Last week, I mentioned that Matsushita might not be getting the respect they deserved with a 45nm process obliterated by Intel’s shadow. I also should acknowledge that I was one of the doubters and expected Intel to not only get to 45nm first but with a considerable lead on second place. Well it turns out that the speculation by Engadget and others coming out of CEATEC was correct. Matsushita (or Panasonic) not only has a real 45nm logic process, but they beat Intel to the market!

Matsushita doesn’t bother with high-k gate dielectrics or metal gate electrodes at 45nm, but they achieve the transistor packing density of the latest technology node. In fact, the Matsushita process beats Intel’s tightest metal pitches. The DVD decoder chip is a complex SoC with over 300 small SRAM arrays scattered around the die. A compact die size of 68 square millimeters certainly would not be possible without a small bit cell design, and Matsushita’s SRAM cell size matches up with Intel. With slightly tighter than 140nm pitch at metals one through four, Matsushita actually has a slight edge over Intel’s 150nm observed pitch.

The UniPhier SoC is truly built to reduce silicon die area and cost. Believe it or not, Panasonic uses it in a video player with a VHS tape bay. That’s something old along with the new in the DMR-XW200V Blu-Ray player. There could be something borrowed as well, but we are still analyzing the device, and I’m not a lawyer.

Finally, let me extend a sincere apology to Matsushita for underestimating their prowess in process technology as well as a hearty congratulations for being the first manufacturer of 45nm logic technology.

Yesterday marked the dawn of a new era of scaling for CMOS devices. I hope that statement fits with all the hype around the launch of the 45nm microprocessor from Intel. In fairness, though, switching to metal gates and high-k dielectrics represents an important milestone in semiconductor technology. Gordon Moore’s well-worn comments are appropriate:

“The implementation of high-k and metal materials marks the biggest change in transistor technology since the introduction of polysilicon gate MOS transistors in the late 1960s.”

Intel released TEM images of its 45nm PMOS transistor. The embedded SiGe source / drains are evident, but we’ve all seen those before. For his keynote, Paul Otellini seemed confident that we could not tell what Intel’s secret sauce in the dielectric and workfunction metals was, but they had something to hide on top of the gate stack. We can’t see the CMP surface, but that’s a no-brainer for a replacement gate (aka gate last) technique. I think they want to keep the capping material on top of the gate electrode hidden until they present at IEDM (Paper 10.2). At about 9:30 on the morning of December 11 in Washington, DC, Kaizad Mistry will open the trench coat on the 45nm HKMG process. Considering the secrecy Intel has been able to maintain on this process, I think the trench coat is a fair reference. Intel deserves full marks for keeping its employees and vendors quiet for so long. Steve Jobs is jealous, I’m sure.

Or maybe he’s not. SI will be opening the kimono on the Penryn this Friday to all our clients participating in the analysis. Intel will still generate lots of excitement at IEDM (at least if you aren’t analyzing 45nm or buying one of our reports).

There’s been much hype and there will be much more.  The Penryn MPU hit Time magazine’s list of best inventions of 2007 along with the iPhone cover girl. Intel may covet the iPhone socket and may well win it for next generation devices, but there may could be another connection to Time’s list. NASA’s methane powered rocket might one day look to the Intel marketing machine as a steady source of fuel.

While attending the IBM and associates Common Technology Platform Forum this afternoon, it occured to me that I was bridging the gap between the design community and trying to get it right, and the failure analysis community that steps in too often to mention in polite company. That’s because I am also in San Jose to attend the International Symposium on Testing and Failure Analysis (ISTFA). The gap is more than a conceptual one as well since there are few if any slick executives at ISTFA. In fact, “engineer” is a word that is spoken in a somewhat unflattering fashion by many ISTFA presenters. But I refuse to hide my iron ring. (Big deal, I know since Canadians are in short supply at these events. Maybe at tonight’s Sharks game, it would be recognized but SI still hasn’t heeded requests to include pro-sports packages into corporate travel arrangements.) Since so many failure analysts are engineers, I guess it’s really designers – not engineers at large – that are the brunt of this abuse.

Intel Fellow Dr. Mario Paniccia enlightened the crowd with Silicon Photonics: Opportunity, Challenges & Applications. Dr. Paniccia is director of the photonics technology lab, but he got his start in quality and reliability at Intel. In fact, this appears to be how Intel decided that optical components on silicon made sense. It was the success of optical fault isolation and analysis tools used in silicon FA that got them thinking. If electro-optical interactions in silicon could be exploited for detecting failures, why not find a way to make photonic devices?

Without going into too much detail (I would not do it justice anyway), waveguides can be built very effectively on SOI. The game-changer for photonics is that silicon has patterning and processing tools available that are leagues ahead of the III-V equipment. As Dr. Paniccia said, the silicon photonics world can “draft” two or three generations behind Moore’s Law and still produce components that are beyond the wildest dreams of traditional photonics providers in terms of booth footprint and cost.

The trick to making this work is to get lasers and detectors onto silicon. Since silicon is an indirect bandgap material, emitters and detectors are better left to the compound semiconductors. But that is not a real set-back to the silicon developers because complicated packaging and assembly is still required of non-silicon components. Intel has developed ways to align multiple InP-based lasers onto their silicon waveguides at the wafer level. This work, done in collaboration with the University of Santa Barbara, has developed 30+ 40Gb/s parallel tranceivers. Get some more details from the Intel blog.

At this time, I would like to pass along my condolences to the III-V photonics community. With the Intel powerhouse on the verge of making your optical components as dirt cheap and tiny as today’s DRAM and flash, I believe your days are numbered.

The new buzz word – acronym actually – coming out of today’s IBM-Chartered-Samsung Common Platform Forum today here in Santa Clara is the term introduced by Qualcomm Senior VP and GM, Behrooz Abdi. His view of the consortium is to create an “integrated fabless manufacturer” or IFM akin to the IDM he means to displace. (Qualcomm has after all surpassed TI in the RF space perhaps leading TI towards its fab-lite ideas.)

IBM and its partners here are putting on a great show. Lunch is over now, and it’s time to get back to the sessions, but I will post more later. Unfortunately, that will be after things shut down back East.

It is a perplexing thing that semiconductor technology requires so mucn investment and innovation, but it is a simple mechanical design that makes one product more useful or attractive to the consumer than another. Think about the swivel disk USB drives, or stiletto type where the connector is pushed out of a sleeve. Convenience is something that is not about the technology node or wafer size but whether your flash drive has a cover you can’t lose.

This confuses the semiconductor analyst and many of the engineers who cram features into smart phones but find little interest outside of the tech community. It’s a problem with a long history amongst techies and geeks. The products we often drool over seem to find little broad-based market appeal. I think it’s high time to tip our hats to the mechanical engineers and designers out there. These are the people that design fantastic plastic cases and switches that not only house the insane feature sets going into consumer products but sometimes even stay working well into the devices’ obsolescence.

Getting back to the USB drive for a second, I shudder to think what ancient technology my 256MB drive (received free at a conference) is built with. But it stores much more than I need to  quickly transfer files between work and home. (I hope my manager is reading this!) But what I might appreciate are the really tangible things. How it feels in my hand or how attractive it is could influence future purchases.

That look and feel is the result of the industrial designers and mechanical engineers. Consider the Sandisk Cruzer Contour drive. It even comes with an atractive faux leather carrying case. But it’s the hideaway USB connector that is the killer technology.

But innovation of design doesn’t require quite so much flash (excuse that pun). Even the Memorex Traveldrive has a cap that stays with the unit so you can’t lose it. I wonder now if there are any retractable pen patents still alive.