SemiSerious

Okay, so this post is a day after the news, but that’s still better than posting beforehand to create the appearance of a scoop. Yesterday, Intel’s much anticipated presentation of their 45nm process was held at IEDM in Washington. Although I suggested last week that Intel would reveal certain details of their process, much of it still remains a mystery to the wider public. Of course, the devices are openly available allowing one to actually see what’s inside. The IEDM paper gives many details about staying on the curve (Moore’s Law, that is) and the transistor performance the 45nm HKMG process achieves. But it’s more than a little short on details of how that performance is enabled. Anyone fortunate enough to analyze one of the Penryn chips could even conclude that Intel was hoping to throw us all off the scent. (I apologize too since my Perler bead model in the photo is also a bit misleading.)

Intel describes the transistor formation as “high-k first and metal gate last.” If last means after sacrificial poly, then that description is not entirely accurate.

But IEDM offers more than the Intel 45nm show. This was even evident even to Popular Mechanics’ blogger who noted that Intel 45nm would be “duelling” with the AMD, IBM, Freescale, Sony and Toshiba announcement about 32nm. I appreciate, though, the fact that neither the “duel” or Intel’s 45nm presentation itself obscured some more futuristic technology for at least this one reporter in DC. Check Popular Mechanics for some pictures and description of Stanford and Bosch spiral sensor arrays and the University of Tokyo “communications sheet” that allows devices placed on it to communicate with one another while receiving power for charging (also on TR today.

As an IEDM outsider this year, I picked the energy harvesting devices session (14) as a must see. Running parallel to the CMOS technology platform session, I’m sure that it was largely overshadowed by the big boys. But many of these concepts will benefit humankind in a variety of ways and arguably more than CMOS IC technology. As most will guess, the harvesting session includes photovoltaics or solar cell technology, one of the hottest and most newsworthy topics of the last year in the semiconductor industry.

Everybody knows about oil crises, global warming and the Kyoto protocol, so alternate energy is really a topic for the mainstream news channels. But micro- and nano-power generation is where it’s at. Or I guess I should say where it will be at. Check some earlier posts to SemiSerious to track down some information in this exciting field. I really think this will be field that enables many amazing devices from multipurpose nanobots in your bloodstream to wide area sensor nets keeping tabs on the population for the large sibling.

At the Common Platform Technology Forum last month, the design for manufacturing (DFM) session message was, “not if but when the industry will have to move to structured gate layouts.” Intel already has.

The industry is at a point where design for variability (DFV) is required. The old approach would be to add margin, but design margining has no scalability and no future.

A better option is to take a DFM approach that creates more litho-friendly designs. Intel has pushed out investment in new lithography tools, keeping their 193nm dry toolset at 45nm. Surely, one outcome of that decision was a requirement to use restricted design rules or a “structured” gate layout to improve yields. There is tangible evidence of this on the Penryn die. The metal gate lines are patterned in regular, parallel patterns to improve both printability and processing to maintain fidelity of the final structures. CMP is obviously a critical step in Intel’s gate last approach, and the structured layout also improves CMP. Filling the narrow trenches with the metal gate material must be easier too when there are fewer nooks and crannies in nice straight gate lines.

In an effort to maintain control of the message as information begins to leak out just before their IEDM presentation on Tuesday, Intel’s Kaizad Mistry provided a few nuggets to Semiconductor International. By restricting design rules to keep poly lines running in a single direction and switching to a wider SRAM architecture, Intel was able to push its SRAM feature size harder, Mistry said, adding that, “Many times, these design changes are beneficial for patterning.”Semiconductor International reports that Intel used double patterning lithography to “square off the ends of the patterns, reducing rounded ends (dogboning) and irregular shapes (icicles).” Looking at the Penryn deprocessed to tungsten metal 1, it is easy to compare the double-patterning used at the metal level to the tungsten trenches where it was not. According to Mistry, “There are benefits in terms of performance and layout density. The trench contact serves as a form of what you might say is local interconnect. And in terms of patterning, it is easier to pattern lines and spaces than a field of holes.”

I’m sure it’s not intentional, but the PMOS image released by Intel is a little misleading. At their paper on Tuesday at IEDM, look for Intel to clarify the situation by showing that the real story of their metal gate is much closer to the hafnium oxide high-k layer.