SemiSerious

At the Common Platform Technology Forum last month, the design for manufacturing (DFM) session message was, “not if but when the industry will have to move to structured gate layouts.” Intel already has.

The industry is at a point where design for variability (DFV) is required. The old approach would be to add margin, but design margining has no scalability and no future.

A better option is to take a DFM approach that creates more litho-friendly designs. Intel has pushed out investment in new lithography tools, keeping their 193nm dry toolset at 45nm. Surely, one outcome of that decision was a requirement to use restricted design rules or a “structured” gate layout to improve yields. There is tangible evidence of this on the Penryn die. The metal gate lines are patterned in regular, parallel patterns to improve both printability and processing to maintain fidelity of the final structures. CMP is obviously a critical step in Intel’s gate last approach, and the structured layout also improves CMP. Filling the narrow trenches with the metal gate material must be easier too when there are fewer nooks and crannies in nice straight gate lines.

In an effort to maintain control of the message as information begins to leak out just before their IEDM presentation on Tuesday, Intel’s Kaizad Mistry provided a few nuggets to Semiconductor International. By restricting design rules to keep poly lines running in a single direction and switching to a wider SRAM architecture, Intel was able to push its SRAM feature size harder, Mistry said, adding that, “Many times, these design changes are beneficial for patterning.”Semiconductor International reports that Intel used double patterning lithography to “square off the ends of the patterns, reducing rounded ends (dogboning) and irregular shapes (icicles).” Looking at the Penryn deprocessed to tungsten metal 1, it is easy to compare the double-patterning used at the metal level to the tungsten trenches where it was not. According to Mistry, “There are benefits in terms of performance and layout density. The trench contact serves as a form of what you might say is local interconnect. And in terms of patterning, it is easier to pattern lines and spaces than a field of holes.”

I’m sure it’s not intentional, but the PMOS image released by Intel is a little misleading. At their paper on Tuesday at IEDM, look for Intel to clarify the situation by showing that the real story of their metal gate is much closer to the hafnium oxide high-k layer.

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