Embedded RAM

For years, there has been speculation that traditional SRAM would be replaced with a denser type of memory for SoC devices. In fact, TI once announced that they would use ferroelectric RAM or FeRAM beginning at 90nm for their devices. Fear of ever-worsening process variability has been widespread. Alas, we have entered the 45nm period, and SRAM continues to be the workhorse of the industry.

I’m not suggesting there has been no competition. Once upon a time, it was popular to use a DRAM cell, hide the refresh inside a circuit macro, and call it 1T-SRAM.

But why have these alternatives either never been used (FeRAM and others), lost favor (as it seems in the case of 1T-SRAM and eFlash), or been relegated to only very high density, very high speed applications (as with DRAM)? But don’t expect an answer, I’m just posing these questions – at least for this week. Winter has weighed me down too much to think about such things.

DRAM has enjoyed some success, so let’s take a closer look. The bits are denser. A DRAM cell occupies only eight times the minimum area unit of a given process technology versus about 120 or more for an SRAM cell. Looking at it this way, SoC DRAM should be a no-brainer right? Wrong. The DRAM is dynamic RAM. That is, leakage in the cell access transistor will erase the contents of the cell. So the cell has to be refreshed. The circuit overhead for cell refresh along with some other operations means that the DRAM taken as a complete circuit macro will only be smaller than an SRAM for densities beyond about 4MB.

Until very recently, SoC DRAM has been narrowly confined to graphics processors from gaming consoles. Microsoft, Nintendo, and Sony game systems have all used graphics engines that integrated large embedded DRAM (eDRAM) arrays onto their chips. The semico’s that actually produced the chips were ATi/NEC, IBM, and Sony/Toshiba. IBM has enjoyed a long history in the development of DRAM and embedded DRAM. IBM invented trench capacitor DRAM, and this type has become the de-facto standard for SoC devices. I say that despite NEC’s stacked capacitor structure used in one of the XBOX 360 chips. In fact, the ATi/NEC chip is a very special case of eDRAM. It’s really more of a DRAM with integrated memory controller. Dick James has some interesting thoughts on eDRAM in game consoles that you can reach with this link.

The Sony gaming consoles are an interesting case study. Consider this. PS2 and PS3 consoles contained graphics engines with eDRAM. However, the hand-held PSP does not. Instead, a commodity DRAM die is packaged, SiP style, along with a pure logic LSI device. You might say that portable devices need to be more energy efficient and would demand the use of single-chip solutions over multiple die which typically suck more power. But there is more price and manufacturing cost pressure on the PSP driving Sony’s choice for the portable platform. High development and process integration costs are certainly limiting the use of eDRAM. I think the lesson from Sony is actually more general and addresses the whole SoC versus SiP debate.

My take is that eDRAM will only ever exist in a couple of places. It will continue to provide extremely large on-chip arrays for memory-hungry special purpose graphics processors. It will also become more common where bits need to be neatly packed along the columns of an LCD driver. But once again, this will only be for extremely memory intensive applications such as mobile drivers with very large color depth.

Other than that, SRAM will reign supreme. For the best example, look at the Qualcomm MSM7500 die micrograph at the top of this post. For a complicated SoC architecture like this, embedding DRAM makes no sense. Another example of SRAM maintaining its foothold is the latest 45nm MPU. Since Intel still did not integrate a memory controller onto the Penryn, the design still relies on a huge 6MB L2 cache, but it’s still good, old-fashioned SRAM.

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