SemiSerious

This week presented interesting news as two image sensor technologies I thought might one day displace traditional types appear to have made breakthroughs on the march to commercialization. NHK showcased an active layer over IC - or AIC -type of sensor while OmniVision announced they would be sampling a backside illuminated - BSI - detector next month. Junko Yoshida’s detailed article on EETimes put me onto the backside scent. 

For the traditional CMOS image sensor (front-side illuminated or FSI to use the OmniVision convention), the ratio of stack height or optical path length to pixel pitch is an important limitation. There are many drivers - both market and technical - for decreasing the pixel pitch of the image sensor. Leaving those aside for now, shrinking active pixel sensor dimensions is a given. Since the active silicon region (or photodiode) where incoming light is converted into electrical energy sits at the bottom of the metal interconnect, it’s easy to see why this dimension receives so much attention. As a result image sensor manufacturers have raced to reduce the height of the interconnect over the photodiode. This is most important with CMOS image sensors (CIS) since CCD’s do not include any processing circuits on the sensing chip. CIS devices often incorporate a great deal of signal processing on the same silicon as the sensor. Increasing integration drives more metal wiring levels if you hope to keep the total chip size under control.

About the time SoC integration on CIS was reaching a peak, a few manufacturers transitioned from aluminum to copper for the interconnect. Copper’s lower resistance allows thinner wires for a given line pitch for the same design target resistance as aluminum. Thinner metals means a shorter optical path to the photodiode. But copper integration is not ideal for image sensors since the barrier levels create unwanted interfaces resulting in reflections and optical system losses. There were also rumours of lower camera module yields for devices built with copper. Whatever the reasons, many manufacturers returned to aluminum and longer optical paths. But a few percent improvement will not eliminate the issues with optical path length, something these two new technologies avoid for the most part.

Both AIC and BSI approaches treat interconnect where it should be - literally the “back end” from the optical point of view. An AIC detector adds active silicon with photodiodes on top of the chip wiring, so light reaches it first. BSI flips the chip allowing light to hit the sensor from the back. Viewing a BSI detector in cross-section, it would like very similar to the traditional FSI device. The only differences is that light enters through the backside of the substrate opposite to the active silicon surface.

Several companies have published work on the AIC approach. The sensor in these cases is most commonly amorphous silicon patterned into detectors after traditional BEOL metal IC processing. These devices employ similar structures and materials to those used in LCD display panels. ST Micro and Samsung have been brewing this type of technology for a while. (ST and Samsung both had multiple presentations at IISW 2007. See my earlier post.)

But the NHK sensor uses an organic light sensitive layer rather than silicon. I have not been able to confirm a connection with FujiFilm, but this sounds a lot like the technology they presented at last year’s IISW. It doesn’t take too much imagination to visualize the organic sensor approach as spreading old school analog film emulsions over a state-of-the-art readout IC.

I guess it’s obvious that substrate processing must be adapted for the BSI device. That is almost assuredly based on SOI technology. The leading SOI substrate provider is Soitec. CEA-LETI spawned another company in the SOI space in 2003. Tracit Technologies offers layer transfer technology to IC’s onto SOI substrates. Last year, they helped e2V bring backside detectors to the “medium volume professional image sensor market.” I think TraciT will be an important factor in getting BSI into the high volume consumer market.

There has been a lot of news this year about the wafer-level camera (WLC) and through-silicon vias (TSV) to facilitate it. Even some reverse engineering blogs have something to say about TSV! BSI offers an interesting packaging option in addition to the many performance advantages as well. It lends itself well to flip-chip packaging. Perhaps the cost adders that have maligned the BSI approach in the press will be more than compensated by the cheaper flip chip packaging it will allow.

OVT now calls this technolgoy “BSI” for back-side imager, but it seems to have been previously called “BID” as I learned at IISW 2007. Dr. Bedaprata Pain should now be very happy that his attempts to jump-start the transition to back-side illumination may have sparked commercialization of the technology.

OmniVision’s PR states:

OmniBSI architecture delivers a number of performance improvements over FSI, including increased sensitivity per unit area, improved quantum efficiency and reduced cross talk and photo response non-uniformity, which all lead to significant improvements in image quality. Since light directly strikes the silicon, the fill factor of the image sensor is significantly improved so as to deliver best-in-class low-light sensitivity. A much higher chief ray angle enables shorter lens heights which in turn allows for thinner camera modules, which are ideal for use in the next generation of ultra-thin mobile phones. Finally, BSI technology affords a much larger aperture size, which allows for lower f stops facilitating the development of better performing camera modules with superior camera performance.

Even though this is written by the spin doctors, their statements are absolutely correct. The improved low-light sensitivity will be especially important for cameraphones as users, and therefore designers, are demanding improvements to images acquired in pubs, restaurants and parties. Nokia made this very clear at Image Sensors Europe, and those sentiments were echoed by a number of sensor manufacturers including Aptina and OmniVision.

As for the suggestion that there is little novelty to the BSI detector approach, I can’t argue that the idea was around for a while (check Stern, Proc. SPIE, vol. 1071, 1989). For example, MIT Lincoln Labs has a long history in this field. But then again, how long did it take the laser to make its way into a useful consumer product?

There are more rumors this week about AMD’s manufacturing strategy. Tony Smith of The Register cited a DigiTimes report that AMD will be adding TSMC as a production partner. Fusion processors are scheduled for late 2009. If you think about it, you could say that AMD already has a long-standing relationship with TSMC. After all, ATI was one of the foundry giants biggest customers for years, and this has continued to manufacture GPU’s at TSMC since AMD acquired them almost two years ago. So it’s not a stretch (or such big news) that AMD would consider moving a chunk of its microprocessor production to TSMC as well.

AMD is part of the Common Platform technology consortium that leverages research and development from IBM and volume manufacturing expertise from Chartered. The idea is sound but may require some more time to mature and pay dividends for some of the partners. I have heard that Chartered’s past experience has been centered around the copy exact mentality and running wafers through without trying to improve yields. If a customer such as AMD developed a new process, it was moved into Chartered ‘as is’ on the identical toolset with no continuous process improvement.

The need to maintain an open dialog between the fab and the design team is now broadly accepted including Chartered, and this has prompted their involvement in the Common Platform. On the other hand, TSMC recognized this need much earlier than their foundry competitors (at least in Asia). TSMC has done an outstanding job of closing the loop between design and fabrication often taking the next step of mask editing for layout optimization to improve the yield of its customers designs. TSMC designs, acquires and maintains a large library of IP cores with guaranteed yield in its fabs. Not only can they provide these IP blocks as plug-in modules to customers, but the knowledge they gained developing those cores can help designers to optimize layouts for leading-edge TSMC processes. TSMC has a knack for squeezing out those last few percent of yield.

But what about SOI at TSMC? The SOI processes used by AMD are tightly bound to IBM and its partners. TSMC has worked on SOI in the past, but I’m sure licensing talks related to SOI will be a big part of any move to TSMC-fabbed MPU’s. Or maybe TSMC will convince AMD to transition MPU chips over to bulk silicon (where the GPU’s are now) and cut Chartered, IBM and the Common Platform out completely. Is that what Hector Ruiz means when he says, “our plans are bold?”
 

From all the rumor and conjecture we hear, AMD’s manufacturing strategy could well be running out of steam. Could this be another case of milking the local government and low-priced labor in a geography and then pulling up stakes once the subsidies run out or local salaries get too high? There are reports of labor strife in Dresden. The days of cheap labor in Eastern Germany are gone and so with them possibly AMD fabs. That would be an unfortunate loss for Europe and AMD.

AMD had success in previous years by creating a superior CPU design to Intel’s. The tables have been turned recently with Intel using their teams in Israel to produce first-class designs. With so much capital and research behind manufacturing at Intel, maybe AMD should re-focus their efforts in design where they have proven that they can outperform their huge rival.

But I think that AMD’s design and manufacturing are both technically sound. The Common Platform Technology consortium with IBM research driving innovation is definitely providing enough horsepower to stay at the leading edge of the technology curve. High volume manufacturing was reliable at Chartered through 90nm and 65nm. Perhaps AMD’s difficulties lie with a marketing or management-level decision to put four processor cores on one die. Intel packages two dual core dies together to create their quad core MPU. Although, there is a slight performance benefit to getting all the cores onto a single piece of silicon, is it really worthwhile in today’s world with very little software written that’s able to take advantage of multi-core processing power? For the kind of performance gains possible, the costs are just too high. Lower yields for a much larger quad core die mean either higher production costs now or waiting to improve yield and pushing out volume production to a later date. Lose money or lose market share, that’s your choice with the bigger chip.

Perhaps AMD has learned some hard lessons regarding procs per die. As Rick Merritt just reported in EETimes, AMD has announced a 12 core server chip that contains two six-pack processor die.

Intel blew it with the Prescott, but grabbed back market share in the server market by adopting AMD’s design strategy. So even when they lost, Intel had enough clout to grab back what it lost while heading back for a ground-up redesign. It’s obviously not fun being in a cage match with Intel every day. AMD deserves respect for staying in there, round after round.

I’m not sure I would go so far as to agree with many of the allegations AMD has made against Intel in the anti-trust suit, but then again, it’s hard to say. Intel is just so big, rich and powerful, there’s a lot they can do. They probably have more PR firms under contract than they can even remember. Even if you argue the allegations of a conspiracy to lock out AMD with the major PC makers, I’m sure you would agree that there has been a lot of bad press circulating about AMD. It never takes much of a spark to create a wildfire of news reports on something like this, but as each flame dies out, it seems that there is a new story popping up somewhere else. Don’t financial analysts have other stocks or markets to consider? Or just maybe there are people working hard to keep up this negative momentum in the press.

Why does it work for Intel - keeping fab operations inside the US? For now, they have that luxury because of overwhelming market share, but I would guess their time will come as well. If AMD can transition successfully to a fab-lite model, perhaps they will grab enough of the microprocessor market to get Intel (or the analysts) talking about fab-lite as well. I hope AMD can increase market share one way or another because competition is a healthy thing - even for Intel.

A couple of my colleagues were surprised to say the least this week when the devices they were working on turned out to be rather elaborate fakes. Or not - I’m not exactly sure.

SI was undertaking a reverse engineering project looking at a certain leading CMOS image sensor supplier’s device who is known to use a certain leading Asian fab to manufacture its devices. Ten units of the chip came from a parts distributor in Hong Kong.

At first glance, the devices appeared as expected. The package was standard-issue for image sensors with hermetically-sealed cover glass over the sensor die. Everything still appeared normal after removing the sensor die from the package. A typical SoC type of image sensor layout was clear with the pixel array occupying about 26% of this 38 square millimeter chip.

But that’s where our expectations diverged from reality.

After dropping one die into acid to remove all the interconnect layers and get a quick look at the active area patterning, the silicon appeared blank. The engineer then quickly beveled the IC in order to expose all of the active layers. Again, there was only whitespace deeper into the chip. Starting with yet another sample from the lot, our lab cross-sectioned through the device. This final step revealed only one metal level, color filter array, and microlenses - no transistors or lower levels of metallization.

A senior process engineer not assigned to the project suggested these devices could be mechanical samples. That seemed reasonable. If you wanted to test a new package type for instance, it might make sense to order a few duds built with only the BEOL processes. Even more believable would be a BEOL-only device for environmental testing since microlens arrays are notoriously sensitive to high temperatures. Increasing adoption of imagers into the automotive industry along with research reports of temperature-hardened microlenses adds some credibility to this idea. (For example, see a TI Japan and Tohoku University paper from IISW 2007 entitled, “A Wide Dynamic Range CMOS Image Sensor with Resistance to High Temperatures.”)

However, the devices we bought were not advertised as mechanical samples but as fully operational image sensors under a leading manufacturers part number. And it wasn’t just one or two devices. The whole lot of 10 appears to suffer the same lack of active circuitry. The distributor is from China, so I know what many of you are thinking - another counterfeit chip scandal is brewing. There’s been a lot made of counterfeiting activity in China. A quick search of that keyword at EETimes will give you dozens of stories to choose from if you want to dive deeper into this murky field.

My best guess at what happened in the present case is that a legitimate order was placed for mechanical samples. But a few “extras” were produced beyond what was required for the environmental testing. Some enterprising worker at the manufacturer decided not to waste the spares and found a discount IC distributor on the lookout for cheap devices.

The first step to uncovering a more complex scandal would be to identify the IC foundry of origin. I happen to know some engineers who have a lot of experience in this field. If they are able to determine that these devices were produced at one of the expected manufacturers main production lines, then the mechanical sample overrun theory would be supported. If not, then maybe this will be the beginning of a bigger story of a semi-serious counterfeiting operation based on chips that could pass only an external visual inspection. Was it was an outfit that only managed to steal one layers worth of design files? Or maybe someone reverse engineered only one level of a legitimate version of this manufacturers device.

This isn’t the first strange case I’ve seen of a partially processed, yet fully packaged chip getting into the distribution channel. It’s unfortunate my memory is so bad that I can’t remember more details of that device which is now buried somewhere deep in the Semiconductor Insights chip graveyard. What I do remember is similar though. Despite containing all the interconnect levels, the polysilicon was an unpatterned, featureless sheet, and there were no vias between metal lines. I guess we weren’t as focussed on counterfeit in those days because it never occurred to me at the time.

My conspiracy theory is that the bean counters took over the fab. Maybe this is the “New Economics of Semiconductor Manufacturing” as described in IEEE Spectrum. Why not save a couple bucks by just avoiding those costly front-end manufacturing steps altogether? After all, with image sensor ASP’s getting continuously hammered, what else can manufacturers do to keep making a buck?