IEDM 2008 Preview

Leaving things until the last minute is certainly nothing new for me, but I might be better off waiting to summarize next week’s IEDM than trying to preview it here. These days, there is a constant flow of negative news in the chip industry and the wider economy, so thinking about the research and development side of things for a while is a welcome break. Those actually at the conference may not have the luxury of avoiding the recessionary indicators since widespread cost-cutting is sure to make the event much smaller than usual. At least moving around at the coffee breaks will be easier.

Back to the concept of the preview, I had the really good fortune to speak directly to both IBM and Intel about their upcoming papers. Mark Bohr promoted presentations from three different technology angles that will appear at IEDM this year. The highlight is certainly the late news paper that Sanjay Natarajan will present. Sanjay is the Manager of Intel’s 32nm CMOS Technology Development and will provide a little more information on what is coming from their second generation HKMG. The emphasis will be on “little.” Intel rarely discloses much about their processes, but they have already released a couple of key metrics:

World’s tightest gate pitch of 112.5nm, and
World’s best drive currents – 1.55µA/µm for NFET’s and 1.21µA/µm for PFET’s.

You may see a pattern here. Intel likes to be way out front when it comes to numbers like this, and they certainly plan and make the investments necessary to achieve and maintain their lead. Last year at the Intel Developer Forum, Sanjay noted that the release of their first 32nm SRAM test chip was only 20 months after the 45nm version – well ahead of Intel’s already aggressive two year cadence for technology node introduction. Based on the combination of their process technology, transistor performance and timing production ramps for these nodes, Mark Bohr believes that Intel is “more than one generation ahead of the rest of the industry.” But even if they won’t reveal details of their 32nm process, Intel never needs to say much to draw a crowd. Whatever it is will be big news at this conference. Intel + 32nm is bound to have everyone buzzing.

The second paper Mark Bohr presented to analysts is about enhancing Intel 45nm for low power and SoC applications. Of course, HKMG can give you very powerful transistors, but it can also give acceptable levels of drive while keeping power consumption way down. Chia-Hong Jan’s 45nm SoC paper will claim that the low power process achieves less than 1nA/µm leakage. That’s bound to help battery life as well as Intel’s push to gain a bigger piece of the hand-held computing market. Atom-based based netbooks are surely not the end game in Intel’s aspirations of becoming more accepted into more mobile and portable platforms. The SoC process includes finger capacitors and high Q inductor elements. I wonder what they will build with this technology. It’s worth a trip to the Intel job board to see what kind of analog and RF people they might be looking for.

The third paper touted by Intel PR for the upcoming IEDM takes a longer view. Marko Radosavljevic’s paper on InSb transistors takes a much longer view of the technology roadmap than the previous two entries. Marko’s talk will build on previous work that disclosed n-channel devices with the IEDM paper in p-channel InSb quantum well transistors. Although they have not integrated the two yet, the goal of this work is to create a complete complimentary logic platform to replace silicon in the 2015 time frame. Intel really takes the very long term view of maintaining Moore’s Law. It’s not just the next few ticks of the tick-tock strategy that keeps them busy. Of course, Intel also does a lot of work with exotic silicon devices like FinFET’s as well, but the new channel materials may end up actually requiring fewer changes to the approach to design and manufacturing of IC’s simply by sticking to a planar technology.

Speaking of upcoming ticks though, IBM is very excited about both its 32nm bulk foundry process and its progress towards a viable 22nm technology. Dr. An Steegen will present a paper outlining key features of IBM’s 32nm bulk process. It will be offered in two versions. The first to ramp will be a low power version. IBM will introduce a high-k metal gate stack for the first time at 32nm. Migrating to HKMG from conventional poly gates with SiON dielectrics offers a very low leakage option. This flavor will not employ any strain engineering to enhance carrier mobility. However, the high performance version adds all the well-known stress elements to increase FET drive current. IBM doesn’t pre-release those numbers, so get to the conference or check back here. Better yet, take a look over at EETimes because Mark LaPedus will be keeping the broader community well informed of all the key developments at IEDM as they occur. Dr. Steegen and her team are rightfully proud of their accomplishment in 32nm. They like to point out that their gate first approach to HKMG allows the freedom of conventional gate layout without the need for restricted design rules required by the replacement gate flow used by Intel.

The IBM team at Albany Nanotech is pumped up about their recent progress toward 22nm. Dr. Bruce Doris believes that the rest of the industry should be too. The team will discuss their world record 22nm SRAM that boasts a cell size less than a tenth of a square micron. Proving that an SRAM cell works at the 22nm built on standard 300mm tools is great news for the whole industry and will ease concerns over extending this conventional memory to future nodes. The IBM 22nm SRAM certainly proves the viability of conventional planar CMOS for the next few years, so neither design nor manufacturing flows need to be turned onto their heads by FinFETs or some other exotic device.

In the technology race between Intel and competitors like IBM and AMD, it often seems to boil down to a choice about what to keep. For Intel at 45nm, they kept dry litho but gave up on conventional layout and moved to a restricted set of design rules with regular parallel patterns to give their existing dry litho tools a chance to keep doing the job. On the other hand, IBM and its technology partners like AMD opted to invest in immersion lithography earlier which allowed them to stick with conventional polysilicon layout rules. But there is not avoiding either of these approaches. Intel is using immersion lithography at 32nm. IBM has talked about restricted design rules and computational lithography to get to 22nm and beyond. That makes it hard to pick the best technology. Or it makes it harder for an analyst to be wrong. Either way, I don’t plan to stick my neck out. My colleagues Ramesh Kuchibhatla and Dr. Vu Ho will be at the conference. Talk to one of them. Both are seasoned technology veterans and not shy about giving you their opinion.

Posted in Event Coverage, Events, Industry News | No Comments »