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Archive for April, 2009

Weak Node

As I mentioned last week, there’s a lot of discussion about half nodes and “weak” nodes for logic technology. There’s no disputing that the semiconductor business ebbs and flows in predictable cycles, so there are points in time where the business climate may just not support gearing up for high volume production. If a downturn coincides with 45nm, then a foundry might want to refer to it as a “weak” node. You could argue that “weak” is more marketing spin than technical description. What makes 45nm less powerful than any other node? Considering Intel 45nm broke onto the scene with metal gates and high-K dielectrics, you might even say that 45nm was really pretty strong.

A more likely explanation is that investor confidence is a bit of an oxymoron these days, so corporate PR needs to avoid any suggestion that there is not enough business to recoup the investment in technology development for a major stop on the Gordon Moore highway. That’s at least part of what is at play at IBM, but its Semiconductor Research and Development Center VP, Gary Patton, was surprisingly forthcoming with Mark LaPedus at EETimes. According to LaPedus’ report, weak economic conditions coupled with leakage issues have refocused IBM onto 32nm. Mid nodes or half nodes are mentioned in Mark’s article in a new way that suggests their increased importance. He suggested that foundry customers would migrate straight to the “32/28nm” and skip the “45/40nm” node.

TSMC may not have been the first at 45nm, but they were the first foundry to the 40nm half node. They are set to do the same according to Electronics Weekly. As David Manners reported from the Globalpress Summit a few weeks ago, Altera asked TSMC for their most aggressive process. For logic, you could easily argue that the roadmap for logic processes belongs to Intel since it enacted the law that its co-founder proposed. Now, it seems that maybe TSMC is trying to draft their own legislation about the introduction of new process technologies.

A second piece in Electronics Weekly described the success of Altera’s FPGA product line. I’ll leave it to others to consider the chicken-and-egg story of the Stratix IV and the TSMC 40nm process that it’s built on. It appears that Altera has the 3G cellular deployment in China to thank. this may turn out to be a great success story for the FPGA versus custom ASIC’s. Maybe it’s even an uplifting bit of business news to think that the Chinese market is so hungry for new phones that the base station manufacturers just can’t wait for new chip designs to supply the demand.

Of course, we are all wondering, “When will this new technology actually hit the street?” As reported by Ron Wilson at EDN, Toppan Executive VP of sales and marketing Mike Hadsell suggests that “there may be significant 28 nm activity by early 2010.” If that’s the case, there may be very little lag between the launch of Intel’s 32nm process later this year and TSMC fabbed chips at 28nm.

Digging deeper into the news archives, Mark LaPedus talked about IBM’s view of the plans for 28nm at TSMC back in September, 2008. At the time, the announcement that they were delaying the roll out of a high-K metal gate process was viewed as “risky” for TSMC becuase it put them “behind” their competitors from Chartered, IBM and Samsung. Now it seems that their focus has been on 28nm all along. TSMC will not directly challenge Intel for the lead in technology, but it sure looks like they will be sticking to the bleeding edge.

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