VLSI 2009 – the actual preview post
Last week I attempted to preview the upcoming VLSI Symposia. The conferences are in Japan this year, and my attention was quickly diverted to the current situation in the Japanese semiconductor industry. With all that off my chest, I am free this week to actually look at some of the papers that will be presented starting June 15 in Kyoto.
Maybe it’s because our industry and the whole economy is in the dumps and consolidation is on everyone’s mind or maybe I just didn’t pay much attention before. Either way, looking through the advance program’s list of authors, I was struck by what I thought were some unlikely collaborators.
Of course, there are the teams of researchers that you expect from the well known business partnerships. There is a joint AMD/IBM paper in the Special Technology Highlights Session on Tuesday. T7-2 is devoted to high-K, metal gate integration for 22nm “and beyond.” The full title gives a nice bump to the word count for this blog:
“Extremely Scaled Gate-First High-k/Metal Gate Stack with EOT of 0.55 nm Using Novel Interfacial Layer Scavenging Techniques for 22nm Technology Node and Beyond”
(I’m hoping these extra words count toward the practice I need to hit whatever the magic number is for writing that’s equivalent to the 10,000 hour principle described by Gladwell in Outliers.)
On the heels of this presentation is another collaborative work from AMD/IBM this time with the addition of Freescale. The title of T7-3 is more compact, but the long list of authors could really help if I was getting paid by the word. (Okay, I know what you’re thinking. If I’m getting paid for this, more than just blog readers are getting ripped off.) If all the contributors attend the session, there might not be room for you, but if not, it’s worth checking out.
The most interesting group of authors from AMD, IBM (TJ Watson Research), and Intel presenting research on a replacement technology for CMOS. It’s pretty academic and includes UCLA and University of Notre Dame participants, but it’s interesting that it’s not a Sematech activity which is where such an unlikely group of allies might be more expected. You could say it was just odd timing to discover this one since it was about the first time I read AMD and Intel in the same sentence after hearing about the EU ruling against Intel that may carry a fine of up to $1.4B if actually imposed. The EU’s fine was, after all, the result of some intense lobbying by AMD to governments in many regions to pay attention to what they claimed were monopolistic business practices. When they get together now, I wonder if these guys talk more about replacements for CMOS or what other jurisdictions might jump on the bandwagon against Intel now that the EU has taken the lead. For my part, I just wonder what happens to that money after it’s collected. Somehow, I doubt it will be used to drive innovation at AMD or anywhere else in order to improve the competitive landscape. I’m sure it will stimulate the economy though, at least for the restaurant industry (or wherever these bureaucrats rack up their expense accounts).
Getting away from politics for a second, the AMD-IBM-Intel paper is part of a special session 6B – “Beyond CMOS.” You could argue that such a session is hardly very special anymore since there have been so many. The larger question is the reason why so many of these panels, conference tracks, events, articles and webinars exist. Is it because judgement day for CMOS is really drawing near? Or is it just good marketing to leverage the fears of an industry with so much capital, manpower and training invested in CMOS technology?
Another presentation that caught my attention (and I wish I could attend) will be given by Samsung. My semiconductor analyst cronies and I have been wondering aloud how much scaling is left in Samsung’s landmark Spherical Recessed Array Transistor (S-RCAT) for DRAM. A change is expected soon since the S-RCAT appears to be approaching the limit at 56nm. Although technologists were impressed by this innovation from Samsung, the name RCAT was not all that exciting. Samsung PR folks are getting set to change that as they seem to be taking a more active role in naming their next technology. Samsung’s newest vertical DRAM cell transistor is going to be known as the TCAT – or Terabit Cell Array Transistor. “Terabit” is impressive sounding both in and outside technical circles. We live in a green age where the term climate change gave way to global warming which has recently been replaced by yet a newer brand name, perhaps tera or terra will manage to grab even more of the spotlight. And I shouldn’t leave out Canadian Football fans in Hamilton, Ontario. Samsung’s new DRAM transistor is bound to play well in TiCat country. (That last bit is included just for Steve Bitton, Industrial Control Design Lines editor at TechOnline and Hamilton TigerCat fanatic.)
In a related story (okay, I admit, that’s stretching things), CEA/LETI and STMicroelectronics will present a paper entitled, “GeOI and SOI 3D Monolithic Cell Integrations for High Density Applications.” If insulating substrates keep going (many don’t believe so) and germanium is adopted for the transistor channels (lots of important people believe this), then there is bound to be confusion down the road between “GeOI” chips and some future “GeoEye” satellite that is meant to track all of our movements. What if they need GeOI chips for the GeoEye satellite? That might be one FoxNews report worth watching.
[...] a good blog post about VLSI Just wanted to point out a blog post by my uber-bloggin colleague Dr. Don Scansen as he previews the upcoming VLSI conference and [...]