SemiSerious

For years the question, “How much is enough?” has been debated regarding NAND flash endurance. How many write cycles do you really need over the lifetime of a camera card or memory stick? How long do you need your portable data to stay intact?

SI’s senior memory analyst, Young Choi, attended the recent Flash Memory Summit in Santa Clara to hear what the vendors are saying about solid-state drives, or SSD’s. As NAND flash prepares to reach out and grab a chunk of the hard disk drive market, it will face even more scrutiny as we will all demand more endurance from the SSD’s that are just beginning to show up in select computers. As Young noted, “The overall impression is that the market is still in its infancy and it will take quite a while before enterprises and consumers adopt systems with SSDs.” And that was certainly the view of Fujitsu who cautiously observed, “the market and consumer are not happy about SSD overall.”

Participants were focused on three areas – performance, endurance and price. Many experts are calling for standardization of SSD performance metrics to eliminate the current state of confusion over SSD performance metrics. That would help avoid the “benchmarketing” we are often forced to suffer in this industry.

When I mentioned the NAND flash endurance debates of the past, I was alluding to the MLC versus SLC wars that have been waged over the years (often with Toshiba and Samsung as the respective combatants). The key information returned from the Summit was based on a usage model of 20GB per day for the typical consumer. This means that MLC NAND flash could provide sufficient lifetimes for consumer SSD products.

Several summit participants tried to predict the future of the SSD market by comparing it to the HDD market of long ago. Expect some major rounds of consolidation considering that there are more than 70 SSD manufacturers today.

But it seems like there is more driving SSD technology than simple bits and drive endurance. There is a shade of green overtaking the SSD conversation. Yes, saving energy and “going green” is a big part of the talk about SSD’s. At the Summit, the local California utility, PG&E, promoted the need to reduce energy demands through technological innovation. Their example was the power consumed by large data centers which can be reduced by transitioning to SSD.

Young mentioned that Intel will have some interesting things to discuss at the Intel Developer Forum August 19 through 21. Intel may concentrate on the controller for SSD, and this may actually be the key component to making NAND work in the SSD. The way operating systems use the hard disk is really tough on flash. For robust SSD’s in our future laptops, we will be relying on Intel and others to implement intelligent control and management of which physical memory locations are used to even out the wear over the whole flash chip over the life of the product. SanDisk has proposed their own version that they are calling LDE or Long Term Data Endurance.

I am in London this week and just wrapped things up at the Intertech-Pira Image Sensor Conference. It was an interesting event with a diverse programme. There was everything from cameraphones to disposable endoscopes to swarms of robotic surveillance insects. Wait. The bugs were just my own nutty comment lifted from IEEE Spectrum. After a day where a single conference session dealt with both cameraphones and tiny cameras placed on the ends of laproscopic surgical instruments, Technology Review was very timely with their news of a cameraphone microscope.

But there was more to the conference than pictures of internal organs (right before lunch, thank you) and discussions of better ways of yanking gall bladders out through small pipes stuck into people.

What was hot? Well HDR - or high dynamic range - was. However, the definition of HDR was nowhere near consensus. HDR capability will be required in both security cameras as well as forward looking driver assistance cameras for cars. The other technology worth watching is backside illuminated imagers. Although it was not a featured topic in a session or even a single paper, it did pop up again in a few interesting places. I got turned onto the backside idea for the first time at IISW last May. Although it was introduced to me relatively recently, it’s been under investigation for a long time. Now it seems like it is picking up some momentum inside image sensor companies and starting to be considered for a potential production technology.

Sensors were not the only interesting discussion. Day two offered everything from the use of Flickr in image enhancement algorithms to shape memory alloys.

Graham Townsend, founder of Spiral Gateway, presented an interesting alternative to ASIC-based  Image Signal Processors (ISP). His team’s “soft” ISP approach avoids the 12 to 18 months lead time to get image processing algorithms hardwired into silicon. The obvious advantage is that the latest algorithms developed can be used in the cameraphone right as it goes into production, and they can be changed even after product launch simply by compiling new C code. Their chip is only slightly larger than a full custom ASIC providing the same processing (16 versus 14 square millimetres including I/O). The idea is based on RICA or re-configurable instruction cell array. Although I know virtually nothing about this architecture or other microprocessor alternatives, I would say the ISP application is only the tip of the iceberg. I can only explain it by borrowing one of Graham’s bullet points - ASIC netlists, wired up ‘on-demand’ in real time. (By the way, the iceberg analogy is quiteappropriate considering that co-chair, Lindsay Grant introduced Townsend by saying that Graham often referred to CMOS image sensors and imaging 10 years ago as just the tip of another iceberg.)

The shape memory alloys are being used by a company called 1…Limited to move the lens in an autofocus system. The alloy wire takes up almost no space (diameter is only 25 microns) inside the module providing space for larger lenses inside smaller modules. The next application of their wire is for adding zoom to future cameraphones.

Professor Raimondo Schettini from the University of Milano (Bicocca) gave an intriguing lecture on image enhancement techniques. These are more than the simple enhancements like automatic face detection or red-eye reduction that are so well known. His group has developed several algorithms for improving images based on decision trees to determine if the image is indoor or outdoor and so on to select the best algorithm based on determining the context in which the photograph was captured. A very interesting extension of that idea was the use of the web and the growing set of not only posted images but also user comments. This is visionary stuff. And I’m not just saying that because  my own presentation suggested that Google Street View might create the next image sensor boom! Professor Schettini intends to use the vast database available on Flickr to selectively apply algorithms to improve the image quality. As one slide pointed out, this is truly “data mining on all the available data.”
 
After IISW last May, this was my second chance to attend a relatively small meeting of image sensor technologists (and marketers as the case was this week). What I have discovered is that image sensor experts are not only extremely talented in their various fields but also a distinctly fun and classy group of people. I think there is a unique level of understanding within the imaging community that each sub-specialty represents only one part of a complex system that creates a final image and that all of the system components in delivering the final product are equally important.

Now an anecdote…I have a long and strange history of people getting my name wrong. I thought “Don” was pretty simple. I don’t know why, but the telephone company has listed me more than once as “Dan.” People I’ve met even several times often prefer “Dan” as well, but I thought everything would be okay here in London. I hoped I would come to a conference with my name correctly indicated in the programme (it was), give out some business cards with my name spelled properly (it was), and show a title slide with my name shown clearly as “Don,” and people would get it right. But I guess my parents were the ones who got it wrong. Within about 90 minutes of presenting yesterday, I was sitting at the same lunch table as an attendee who referred to me as “Dan the Insights guy.” I hope it doesn’t stick.

That’s all for Dan from London. (Well, if you can’t beat ‘em…)

Okay, so this post is a day after the news, but that’s still better than posting beforehand to create the appearance of a scoop. Yesterday, Intel’s much anticipated presentation of their 45nm process was held at IEDM in Washington. Although I suggested last week that Intel would reveal certain details of their process, much of it still remains a mystery to the wider public. Of course, the devices are openly available allowing one to actually see what’s inside. The IEDM paper gives many details about staying on the curve (Moore’s Law, that is) and the transistor performance the 45nm HKMG process achieves. But it’s more than a little short on details of how that performance is enabled. Anyone fortunate enough to analyze one of the Penryn chips could even conclude that Intel was hoping to throw us all off the scent. (I apologize too since my Perler bead model in the photo is also a bit misleading.)

Intel describes the transistor formation as “high-k first and metal gate last.” If last means after sacrificial poly, then that description is not entirely accurate.

But IEDM offers more than the Intel 45nm show. This was even evident even to Popular Mechanics’ blogger who noted that Intel 45nm would be “duelling” with the AMD, IBM, Freescale, Sony and Toshiba announcement about 32nm. I appreciate, though, the fact that neither the “duel” or Intel’s 45nm presentation itself obscured some more futuristic technology for at least this one reporter in DC. Check Popular Mechanics for some pictures and description of Stanford and Bosch spiral sensor arrays and the University of Tokyo “communications sheet” that allows devices placed on it to communicate with one another while receiving power for charging (also on TR today.

As an IEDM outsider this year, I picked the energy harvesting devices session (14) as a must see. Running parallel to the CMOS technology platform session, I’m sure that it was largely overshadowed by the big boys. But many of these concepts will benefit humankind in a variety of ways and arguably more than CMOS IC technology. As most will guess, the harvesting session includes photovoltaics or solar cell technology, one of the hottest and most newsworthy topics of the last year in the semiconductor industry.

Everybody knows about oil crises, global warming and the Kyoto protocol, so alternate energy is really a topic for the mainstream news channels. But micro- and nano-power generation is where it’s at. Or I guess I should say where it will be at. Check some earlier posts to SemiSerious to track down some information in this exciting field. I really think this will be field that enables many amazing devices from multipurpose nanobots in your bloodstream to wide area sensor nets keeping tabs on the population for the large sibling.

At the Common Platform Technology Forum last month, the design for manufacturing (DFM) session message was, “not if but when the industry will have to move to structured gate layouts.” Intel already has.

The industry is at a point where design for variability (DFV) is required. The old approach would be to add margin, but design margining has no scalability and no future.

A better option is to take a DFM approach that creates more litho-friendly designs. Intel has pushed out investment in new lithography tools, keeping their 193nm dry toolset at 45nm. Surely, one outcome of that decision was a requirement to use restricted design rules or a “structured” gate layout to improve yields. There is tangible evidence of this on the Penryn die. The metal gate lines are patterned in regular, parallel patterns to improve both printability and processing to maintain fidelity of the final structures. CMP is obviously a critical step in Intel’s gate last approach, and the structured layout also improves CMP. Filling the narrow trenches with the metal gate material must be easier too when there are fewer nooks and crannies in nice straight gate lines.

In an effort to maintain control of the message as information begins to leak out just before their IEDM presentation on Tuesday, Intel’s Kaizad Mistry provided a few nuggets to Semiconductor International. By restricting design rules to keep poly lines running in a single direction and switching to a wider SRAM architecture, Intel was able to push its SRAM feature size harder, Mistry said, adding that, “Many times, these design changes are beneficial for patterning.”Semiconductor International reports that Intel used double patterning lithography to “square off the ends of the patterns, reducing rounded ends (dogboning) and irregular shapes (icicles).” Looking at the Penryn deprocessed to tungsten metal 1, it is easy to compare the double-patterning used at the metal level to the tungsten trenches where it was not. According to Mistry, “There are benefits in terms of performance and layout density. The trench contact serves as a form of what you might say is local interconnect. And in terms of patterning, it is easier to pattern lines and spaces than a field of holes.”

I’m sure it’s not intentional, but the PMOS image released by Intel is a little misleading. At their paper on Tuesday at IEDM, look for Intel to clarify the situation by showing that the real story of their metal gate is much closer to the hafnium oxide high-k layer.

While attending the IBM and associates Common Technology Platform Forum this afternoon, it occured to me that I was bridging the gap between the design community and trying to get it right, and the failure analysis community that steps in too often to mention in polite company. That’s because I am also in San Jose to attend the International Symposium on Testing and Failure Analysis (ISTFA). The gap is more than a conceptual one as well since there are few if any slick executives at ISTFA. In fact, “engineer” is a word that is spoken in a somewhat unflattering fashion by many ISTFA presenters. But I refuse to hide my iron ring. (Big deal, I know since Canadians are in short supply at these events. Maybe at tonight’s Sharks game, it would be recognized but SI still hasn’t heeded requests to include pro-sports packages into corporate travel arrangements.) Since so many failure analysts are engineers, I guess it’s really designers - not engineers at large - that are the brunt of this abuse.

Intel Fellow Dr. Mario Paniccia enlightened the crowd with Silicon Photonics: Opportunity, Challenges & Applications. Dr. Paniccia is director of the photonics technology lab, but he got his start in quality and reliability at Intel. In fact, this appears to be how Intel decided that optical components on silicon made sense. It was the success of optical fault isolation and analysis tools used in silicon FA that got them thinking. If electro-optical interactions in silicon could be exploited for detecting failures, why not find a way to make photonic devices?

Without going into too much detail (I would not do it justice anyway), waveguides can be built very effectively on SOI. The game-changer for photonics is that silicon has patterning and processing tools available that are leagues ahead of the III-V equipment. As Dr. Paniccia said, the silicon photonics world can “draft” two or three generations behind Moore’s Law and still produce components that are beyond the wildest dreams of traditional photonics providers in terms of booth footprint and cost.

The trick to making this work is to get lasers and detectors onto silicon. Since silicon is an indirect bandgap material, emitters and detectors are better left to the compound semiconductors. But that is not a real set-back to the silicon developers because complicated packaging and assembly is still required of non-silicon components. Intel has developed ways to align multiple InP-based lasers onto their silicon waveguides at the wafer level. This work, done in collaboration with the University of Santa Barbara, has developed 30+ 40Gb/s parallel tranceivers. Get some more details from the Intel blog.

At this time, I would like to pass along my condolences to the III-V photonics community. With the Intel powerhouse on the verge of making your optical components as dirt cheap and tiny as today’s DRAM and flash, I believe your days are numbered.

The new buzz word - acronym actually - coming out of today’s IBM-Chartered-Samsung Common Platform Forum today here in Santa Clara is the term introduced by Qualcomm Senior VP and GM, Behrooz Abdi. His view of the consortium is to create an “integrated fabless manufacturer” or IFM akin to the IDM he means to displace. (Qualcomm has after all surpassed TI in the RF space perhaps leading TI towards its fab-lite ideas.)

IBM and its partners here are putting on a great show. Lunch is over now, and it’s time to get back to the sessions, but I will post more later. Unfortunately, that will be after things shut down back East.

Trying to mute the old joke that compound semiconductors are the technology of the future and always will be, Dr. Vu Ho recently attended the 2007 International Conference on Compound Semiconductor Manufacturing Technology. The III-V compounds and related materials such as GaAs, GaN and InP have for years been a mainstay of advanced platforms in military and aerospace applications. However, they have not penetrated deeply into the high volume consumer segment that gets executives and investors salivating.

The higher performance offered by the “un-silicon” materials have been well known for many years. Higher carrier mobilities and semi-insulating substrates enable transistors and circuits to operate at higher frequencies and with lower losses (see more details here). For many years, the competition for maximum operating frequencies - f_T and f_MAX - put III-V’s well ahead and kept silicon devices out of the running. In the lucrative cell phone portion of the radio frequency market, compound devices established and maintained a foothold. Those components are all related to the RF front-end. Duplexer filters, switches, output power amplifiers, and receiver amplifiers (LNA’s) were all once III-V based. The first erosion of this share was still a compound, but still silicon-based, as silicon-germanium - SiGe - grabbed a piece of the power amplifier market.

Unfortunately for the III-V community, the huge momentum and power of the silicon world continued to push into this space. In the quest for becoming all-digital, today even low-power stages of the RF path are in digital CMOS. There is even an RF switch in Si - albeit on sapphire. In fact, aggressive scaling CMOS transistor dimensions has driven the speed performance to near III-V levels with all competitors reaching hundreds of gigahertz.

Despite the switching speed, transistor density, and relative ease of integrating many functions in one technology platform, CMOS may not win out. Dr. Ho points out that the breakdown voltage and power handling limitations of silicon devices (including SiGe) will limit their march to higher operating frequencies. According to Dr. Ho, the future of III-V devices looks bright.

Power up.

A couple of weeks ago, my good friend and semiconductor analysis colleague, Mark Chambers, attended the IITC in San Francisco. The sessions were held from June 4 to 6 at the Hyatt Regency at San Francisco Airport. Because the dates spanned my wedding anniversary and wife’s birthday and the conference site was far from downtown, I could not attend and Mark has promised not to engage in any “San Francisco” humour.

I talked to Mark about the IITC, and he provided me the following thoughtful and insightful comments.

DS: So Mark, do you have any comments about the conference beyond what I just read at Semiconductor International?

MC: You know how you can witness an event, spend a little time digesting it, then read an article about it and wonder if you were at the same event as the author of the article?

DS: I have the same experience if I watch an entire hockey game on TV and then see the highlights on the sports news.

MC: This article suggests that the “popular” issue of the day was 3-D integration. There were a number of interesting papers presented on the topic, including one from IBM where they mounted SRAM over an 80 core processor and made direct connection to a specific core. LETI presented, as they did last year, their scheme for 3D which uses copper “nails” which is really a variation on the through silicon via (TSV also refferred to as ISV in the article hyperlinked above), although with different processing steps.

But I don’t feel it was any more popular than other themes in the conference. In fact I would have thought there was more attention paid to the papers on low-k including the reliability issues (because there are many).

Dan Edelstein - the manager of the department that made the press release about IBM’s air gap - made a presentation that was broad in the technologies covered, but would only reveal the same info that was in the press release. A paper on IBM’s air gap will be presented at the Advanced Metallization Conference in October. Dan Edelstein will also be giving a tutorial session at that conference.

As a general comment, the papers presented this year seemed like a bit of rehash of last year, with some refinements thrown in. I sense a growing cynicism about whether we’ll see an integrated low-k in production that is less than 2.2 (obviously there is skepticism about IBM’s air/vacuum as a viable dielectric) . Overall, I was fascinated by most of the papers presented as they focused in on the practical issues of following the ITRS. I got the impression that there was no further discussion about the longevity of Moore’s Law, rather, there was a lot of imagination about what happens after its collapse. Only 2 papers on CNTs appeared this year.

DS: What was the attendance like? 

MC: I don’t have actuals but I think there were more there than last year. I’m guessing closer to 1000 which would put it at its highest attendance ever. 

DS: What type of attendees were most in evidence - students, engineers, management etc?

MC: The majority were engineering types by my guesstimates with some management and most of the posters by grad students.

DS: Were most of the attendees North American, or what guesstimate would you make of the breakdown - Asia, US, Europe?

MC: There was a strong representation from the Pacific Rim and Europe, combined probably 50%, the remainder from North America.   When I think about it China (unless you include TSMC and UMC) was conspicuously absent, at least from the list of presenters anyways. 

DS: What was the buzz?

MC: IBM’s press release on AGE (air gap exclusion) was obviously on a lot of people’s minds due to the integrity issues associated with it, but everyone from IBM was obviously told to stay mum on the subject. I had lunch with one of the team members and couldn’t pry anything out of him (discreetly, of course).Other papers on AGE included the traditional pinch off method with CVD but there was a really interesting method presented by NXP/Dow that included the use of a thermally degradable dielectric to produce voids that, if it worked as claimed, circumvented the IBM problem with mis-aligned vias.

DS: What technology seemed to attract the most attention?

MC: Not an easy question to answer. In general the audience was unemotional (refer to earlier comments on attendance). Many papers only got questions because of the long pause waiting for questions. Wafer to wafer integration (or chip to chip) seems to be emerging as a given. One paper suggested it was no longer an innovation but rather an evolution.

DS: What sessions did you attend?

MC: All presentations were in series. I went to all of them.

DS: Good answer in case your manager reads this. Which was the most interesting session?

MC: I’m fascinated by the idea of AGE. It’s interesting to watch the various approaches taken to its integration - nothing has been presented that includes data on reliability after CMP or packaging. Throw 3D on top of that (literally) and it will be interesting to see if it makes it to production. There were only 3 papers on it this year and IBM seems to be the furthest along in development (at least, according to the press). I’m aware that AGE is an old technology in some ways but so much has changed since it’s inclusion in devices from years ago. The thermally degrading dielectric looks interesting. 

Dan Edelstein made the IBM presentation that touched on AGE and was quite communicative (except with reference to AGE).

DS: What seemed to be the most popular session?

MC: I don’t recall a most popular.

DS: Hmmm… Okay, so what papers attracted the most questions?

MC: When Dan Edelstein presented his paper on advanced Cu metallization, he was able to stickhandle like Sid the Kid (DS - if you don’t get the hockey reference please link here) to avoid those referring to AGE. There were lots of questions on the thermally degrading dielectric as well.

DS: Which companies attendees seemed to be asking the most questions? 

MC: There were 3 people who were consistently asking questions, and the cynic in me thought that it was merely an attempt to get air time for themselves or their company.

DS: What technology was the hottest in terms of the number of papers?

MC: At a first glance, I would say that there were roughly an equal number of presentations surrounding 3 topics:

• lowering k in dielectrics,
• decreasing R in the metal lines and the last,
• how the first two affect reliability

DS: What company was the most prolific at the conference?

MC: I would say it’s between IMEC, Crolles2 Alliance (STM)  and Freescale. 

DS: Mark, that was great. Thanks for your time, but most of all, thank you for your analysis. You really cut through a lot of the bull that someone attending the event might have to suffer. 

Easier than choosing a wine for shellfish was my decision to attend the 2007 International Image Sensor Workshop held last week in beautiful (literally - see the translation) Ogunquit, Maine. The huge lobster was served up with an even bigger dose of the latest research in imaging technology. The workshop - formerly known as CCD and AIS - is small, but kept that way to provide an open and friendly atmosphere for the brightest minds in imaging technology. Registration was filled within two days, well before I could respond. Fortunately, our work on Scanning Capacitance Microscopy (SCM) was accepted as a poster presentation.

Three relatively new ideas appear poised to challenge the CMOS image sensor (CIS) used today everywhere from Canon professional cameras to toys. In no particular order

• Back-side illumination (BID)
• Active layer over IC (AIC), and
• Single Photon Avalanche Detectors (SPAD)

have each progressed to a point where they should be taken seriously as mainstream contenders. Conceptually, each has well-known advantages over the standard (CIS) currently in production where the photosensitive element converts light into electrical charge only after the photons have traversed a thick stack required for the interconnect levels of CIS or any other IC. Standard CIS designs enjoy a big development, mass production, and (probably most importantly) market head-start. Scaling of the CIS pixel is feasible for the next two generations - 1.4 and 1µm. Beyond that, one of these newcomers will likely carry the torch.