SemiSerious

Toshiba's LaAlO3/SrGeX/Ge p-MISFET Gate Stack

I mentioned elsewhere that Intel’s approach of removing the oxide interlayer prior to high-K dielectric deposition was a significant advance on the road to scaling HKMG processes for the 16nm node.  This  joint effort with Sematech and UT Dallas will be presented at VLSI Technology Symposium 2009. Intel’s oxide-less gate stack technique might be signaling the direction they will be taking for future high-K processing which has a big impact on the rest of the logic manufacturers.

Although I overlooked the non-silicon channel transistor presentations at VLSI 2009, they are certainly a serious contender for future generations like 16nm. Intel themselves spend a great deal of effort seeking a silicon channel replacement. Many of my trusted colleagues believe that a new material will displace silicon for the transistor channel thereby extending the scalability of planar complimentary logic and avoiding the use of multiple gated, vertical channel transistors such as the FinFET. Of course, it’s a dangerous game to point to one Intel paper about technology that’s three nodes down Sheriff Moore’s road when Intel always explores as many technology options as possible before deciding on a direction for future production.

Intel has been busy pursuing possible replacements for silicon as the channel material for transistors., but they certainly aren’t the only ones as Toshiba’s presentation Monday afternoon in Kyoto proves.

In Session 4B devoted to the germanium MOSFET, Toshiba will present “New Approach to Form EOT-Scalable Gate Stack with Strontium Germanide Interlayer for High-k/Ge MISFETs.” The Toshiba paper claims the highest ever hole mobility in a p-channel FET with a peak value quoted of 481cm2/Vs. With only the abstract and the TEM image provided in the Toshiba release, it’s difficult to say how close they are to providing a viable solution for the equivalent oxide thickness (EOT) target of 0.5nm for the 16nm logic generation. The press release reports the cost of the strontium germanide interlayer is to increase the EOT by “only 0.2nm at the most.” It appears that the gate stack reported by Toshiba achieves a total EOT of “as thin as around 1nm.”

Toshiba has clearly done some great work in this area. They have also clearly demonstrated the LaAlO3/SrGeX/Ge p-MISFET as a technology option. But there are many hurdles standing between this work and getting this gate stack ready for the 16nm node. There appears to be less standing in the way of the Intel zero SiOx interface stack which claims an EOT of 0.59nm. That Intel-Sematech-UT Dallas paper will be presented in the Advanced Gate Stacks Session (3A) just a couple of hours before Toshiba.

One thing I really like about this paper is its return to the term MISFET which was sadly replaced long ago by the now familiar MOSFET.  For the PR professional, it’s all too close to misfit, of course, but in this new age of non-oxide gate dielectrics and even non-silicon channel materials, a more generic term is needed. Oddly, even the session title for Toshiba’s paper is “Ge MOSFET,” but as their abstract says, the strontium-germanide interlayer avoids the low-K oxides of germanium for the gate dielectric in their germanium channel devices. Still, I hope that even if an oxide ends up in the mix for whatever direction the industry widely adopts, we can keep MISFET because geeks – especially semicon geeks – like to think of themselves at least a little bit like misfits.

In the TechInsights tradition, every attempt is made to inspire those designers, engineers and builders who actually do the work of creating technology. To highlight this, a special awards ceremony was held recently in San Francisco. As many of you know, Semiconductor Insights has offered leading technology companies a chance to showcase their best efforts through the Insights Awards which have been handed out to deserving products for many years. As part of the larger TechInsights family, the SI Insight Awards are now presented along with the EETimes ACE Awards at the Embedded Systems Conference (ESC) organized by the TechInsights events team.

The Insight Awards is a year-long process whereby companies who feel their chips are worthy of recognition provide them to the Semiconductor Insights’ crack technology analysis team. After analyzing the performance, circuit architecture and manufacturing processes of the nominees, several sessions are held where the lead analysts present the case for the finalists in each category. The result of the intense analytical scrutiny and many heated debates is our list of winners for this year.

The Insight Award for Most Innovative DRAM technology was given to Micron for their 50nm 1Gb DDR2. If you want to learn more about this most advanced RAM, the best place to start is a great Carl Wintgens article on EETimes.

In a world dominated by iPods and portable media, the award for Most Innovative Non-Volatile Memory obviously holds special distinction (as well as well as contributing extra heat to the winners debates). This year’s very worthy recipient is Toshiba for their 43nm 16Gb NAND flash.

The third device category award in 2009 was presented for the Most Innovative Mobile Processor. The winner was Intel for the Atom processor. Who can argue? Intel devices power the lion’s share of netbooks, the hottest computing platform currently on the market. Not only that, but Intel is leading this charge with the most advanced logic process available today – its 45nm High-K metal gate technology.

And finally the award closest to my heart, for Most Innnovative Process Technology, went to IMFT for its 34nm, 32Gbit MLC, NAND Flash. Since this is an Intel-Micron JV, the Process Technology Award made it two each for both Intel and Micron. As SI’s GM, Emil Alexov pointed out at the ceremony, this is the first product beyond 40nm that we have analyzed. That’s quite a milestone, and it’s no surprise that it is was achieved through the collaboration of the likes of Intel and Micron.

For more a great roundup of ESC and the EETimes ACE Awards and the gala evening, your best bet is to go to see Junko Yoshida’s article on EETimes. The full list of winners is here and the photo gallery of the presentations is also available. The ACE presentations at ESC 09 included some special IEEE ACE honors as well. Please go to the excellent Spectrum Tech Talk blog to get their angle on the event.

So if you won for 2009, there’s no time to lose. Contact the awards coordinator (cystalc@semiconductor.com) to submit your best for 2010. If you didn’t win, our analysis team certainly did not minimize your accomplishments. There were many worthy finalists. Picking the winner was nothing close to easy. (If you read a previous post, you may have heard that it was a “long and sometimes arduous” process.) But if seeing your least favorite competitor receiving the championship trophy left a bad taste in your mouth, what better time is there to let us know why you deserve the crown in 2010?

Looking forward in the current economic climate is so depressing, it’s worth a look back at an event from a couple of weeks ago – ISSCC. I had the opportunity to stay in snowy Ottawa while getting updated on the events of the week remotely by three of the SI engineering team.

Aaron Murray pointed out the qualities he looks for in a great plenary talk. These keynotes need to do more than kick off the conference, get everyone into one auditorium for things like awards presentations, and showcase a few big names in the industry. In a word, the plenary talks need to inspire. It’s great to have a leading researcher from a big organization talk about their world leading researcher, but there’s lots of time for that kind of talk in the other sessions.

This year, it seems everyone agreed that IBM Fellow John Cohn’s, Kids today! Engineers Tomorrow? was a great plenary. I think it inspired our own engineers along with Dylan MacGrath whose excellent piece on Cohn’s message appeared in EETimes.

As for the rest of the ISSCC, it’s been more than adequately covered although there is certainly enough there to keep a blogger in business for a very long time (if he has the time. that is). But there was one other key message returned by our own team.

ISSCC organizers should take note of the best observation coming out of their conference. As one of our engineers noted, it’s time for ISSCC to take a page out of the playbook used at both the VLSI Symposium and IEDM. Provide beer and wine before the forums and panels. When it’s time for debate and discussion of the hot topics of the day, it’s definitely more fun for everyone if not more valuable if both the participants and audience are more relaxed. A little free flowing alcohol helps the stereotypical introverted engineer which means less time at the microphone for all those blowhards who just want to sound smart in front of the big crowd. (Ya, you know who you are.)

Considering this won’t go up until the third day of the conference, it just wouldn’t be right to call this “a preview.” However, last week, I had a chance to get just that from Mark Bohr as he provided an overview of Intel’s contribution to this year’s ISSCC program. Intel is very well-represented at the conference with a total of 15 papers including four of eight in the microprocessor session.

Although, I will not be attending the conference, I am receiving timely updates from our trio of engineers who are at ISSCC right now. Aaron Murray, James Bull, and Mohammad Ahmad are doing a great job of keeping everyone back here in Ottawa up-to-date on the happenings in San Francisco (at least the stuff that’s part of the official ISSCC agenda).

Mark Bohr’s plenary ended before I posted this, so there will soon be lots of places to find a digest of what he presented. The main point is that Intel is moving considerable effort into system-on-chip (SoC) development. As Mark showed, today’s microprocessors are actually really complex SoC devices incorporating several formerly discrete chipset components into a single IC. For example, the Core i7 – or Nehalem – design integrates the DRAM controller and DDR3 I/O’s. Intel is presenting more on Nehalem at the conference. Intel is looking to markets beyond the traditional PC to new, smarter mobile computing platforms. Mark summed it up like this: “Intel is no longer a one-size-fits-all company.”

Looking back, it’s interesting to recall a couple of events. First there was the great debate between TI on the SoC team and Intel on the system-in-package (SiP). At the time (I can’t recall how many years ago), Intel believed that it would be more cost-effective to bring various functionality together inside a package rather than monolithically on a single piece of silicon. Second was Intel’s XScale product line. XScale devices were once a hot topic amongst mobile device developers. But Intel sold the line to Marvell two-and-a-half years ago. What makes Intel circle back to SoC devices targeted beyond the traditional PC? Well, after the dust had settled on the Intel-TI SiP v. SoC debate and the XScale selloff, Apple introduced the iPhone. It’s success provided two key bits of information. First, it was possible for a smart phone to gain serious mass market appeal. Second, the iPhone suggested that a pocketable device was on the verge of being a serious computing platform. Now Intel returns to SoC, and it certainly has the manufacturing prowess to have a big impact in this space. Incidentally, part of Mark Bohr’s presentation touched on continued integration using the Atom core as a building block. Perhaps Intel intends to compete with ARM rather than license their technology as they did in the past with the XScale devices.

The bottom line is that Intel’s renewed interest in SoC technology is going to accelerate the development of ultra-portable computing platforms. Declining sales of the traditional desktop pc are fueling Intel’s move towards other markets. Growth in netbook sales and sockets for the Atom and similar devices are offsetting a lot of the loss in demand for more powerful microprocessors. But the netbook is only an transitional product. Computing is going more portable, and Intel will be ready.

Leaving things until the last minute is certainly nothing new for me, but I might be better off waiting to summarize next week’s IEDM than trying to preview it here. These days, there is a constant flow of negative news in the chip industry and the wider economy, so thinking about the research and development side of things for a while is a welcome break. Those actually at the conference may not have the luxury of avoiding the recessionary indicators since widespread cost-cutting is sure to make the event much smaller than usual. At least moving around at the coffee breaks will be easier.

Back to the concept of the preview, I had the really good fortune to speak directly to both IBM and Intel about their upcoming papers. Mark Bohr promoted presentations from three different technology angles that will appear at IEDM this year. The highlight is certainly the late news paper that Sanjay Natarajan will present. Sanjay is the Manager of Intel’s 32nm CMOS Technology Development and will provide a little more information on what is coming from their second generation HKMG. The emphasis will be on “little.” Intel rarely discloses much about their processes, but they have already released a couple of key metrics:

World’s tightest gate pitch of 112.5nm, and
World’s best drive currents – 1.55µA/µm for NFET’s and 1.21µA/µm for PFET’s.

You may see a pattern here. Intel likes to be way out front when it comes to numbers like this, and they certainly plan and make the investments necessary to achieve and maintain their lead. Last year at the Intel Developer Forum, Sanjay noted that the release of their first 32nm SRAM test chip was only 20 months after the 45nm version – well ahead of Intel’s already aggressive two year cadence for technology node introduction. Based on the combination of their process technology, transistor performance and timing production ramps for these nodes, Mark Bohr believes that Intel is “more than one generation ahead of the rest of the industry.” But even if they won’t reveal details of their 32nm process, Intel never needs to say much to draw a crowd. Whatever it is will be big news at this conference. Intel + 32nm is bound to have everyone buzzing.

The second paper Mark Bohr presented to analysts is about enhancing Intel 45nm for low power and SoC applications. Of course, HKMG can give you very powerful transistors, but it can also give acceptable levels of drive while keeping power consumption way down. Chia-Hong Jan’s 45nm SoC paper will claim that the low power process achieves less than 1nA/µm leakage. That’s bound to help battery life as well as Intel’s push to gain a bigger piece of the hand-held computing market. Atom-based based netbooks are surely not the end game in Intel’s aspirations of becoming more accepted into more mobile and portable platforms. The SoC process includes finger capacitors and high Q inductor elements. I wonder what they will build with this technology. It’s worth a trip to the Intel job board to see what kind of analog and RF people they might be looking for.

The third paper touted by Intel PR for the upcoming IEDM takes a longer view. Marko Radosavljevic’s paper on InSb transistors takes a much longer view of the technology roadmap than the previous two entries. Marko’s talk will build on previous work that disclosed n-channel devices with the IEDM paper in p-channel InSb quantum well transistors. Although they have not integrated the two yet, the goal of this work is to create a complete complimentary logic platform to replace silicon in the 2015 time frame. Intel really takes the very long term view of maintaining Moore’s Law. It’s not just the next few ticks of the tick-tock strategy that keeps them busy. Of course, Intel also does a lot of work with exotic silicon devices like FinFET’s as well, but the new channel materials may end up actually requiring fewer changes to the approach to design and manufacturing of IC’s simply by sticking to a planar technology.

Speaking of upcoming ticks though, IBM is very excited about both its 32nm bulk foundry process and its progress towards a viable 22nm technology. Dr. An Steegen will present a paper outlining key features of IBM’s 32nm bulk process. It will be offered in two versions. The first to ramp will be a low power version. IBM will introduce a high-k metal gate stack for the first time at 32nm. Migrating to HKMG from conventional poly gates with SiON dielectrics offers a very low leakage option. This flavor will not employ any strain engineering to enhance carrier mobility. However, the high performance version adds all the well-known stress elements to increase FET drive current. IBM doesn’t pre-release those numbers, so get to the conference or check back here. Better yet, take a look over at EETimes because Mark LaPedus will be keeping the broader community well informed of all the key developments at IEDM as they occur. Dr. Steegen and her team are rightfully proud of their accomplishment in 32nm. They like to point out that their gate first approach to HKMG allows the freedom of conventional gate layout without the need for restricted design rules required by the replacement gate flow used by Intel.

The IBM team at Albany Nanotech is pumped up about their recent progress toward 22nm. Dr. Bruce Doris believes that the rest of the industry should be too. The team will discuss their world record 22nm SRAM that boasts a cell size less than a tenth of a square micron. Proving that an SRAM cell works at the 22nm built on standard 300mm tools is great news for the whole industry and will ease concerns over extending this conventional memory to future nodes. The IBM 22nm SRAM certainly proves the viability of conventional planar CMOS for the next few years, so neither design nor manufacturing flows need to be turned onto their heads by FinFETs or some other exotic device.

In the technology race between Intel and competitors like IBM and AMD, it often seems to boil down to a choice about what to keep. For Intel at 45nm, they kept dry litho but gave up on conventional layout and moved to a restricted set of design rules with regular parallel patterns to give their existing dry litho tools a chance to keep doing the job. On the other hand, IBM and its technology partners like AMD opted to invest in immersion lithography earlier which allowed them to stick with conventional polysilicon layout rules. But there is not avoiding either of these approaches. Intel is using immersion lithography at 32nm. IBM has talked about restricted design rules and computational lithography to get to 22nm and beyond. That makes it hard to pick the best technology. Or it makes it harder for an analyst to be wrong. Either way, I don’t plan to stick my neck out. My colleagues Ramesh Kuchibhatla and Dr. Vu Ho will be at the conference. Talk to one of them. Both are seasoned technology veterans and not shy about giving you their opinion.

For years the question, “How much is enough?” has been debated regarding NAND flash endurance. How many write cycles do you really need over the lifetime of a camera card or memory stick? How long do you need your portable data to stay intact?

SI’s senior memory analyst, Young Choi, attended the recent Flash Memory Summit in Santa Clara to hear what the vendors are saying about solid-state drives, or SSD’s. As NAND flash prepares to reach out and grab a chunk of the hard disk drive market, it will face even more scrutiny as we will all demand more endurance from the SSD’s that are just beginning to show up in select computers. As Young noted, “The overall impression is that the market is still in its infancy and it will take quite a while before enterprises and consumers adopt systems with SSDs.” And that was certainly the view of Fujitsu who cautiously observed, “the market and consumer are not happy about SSD overall.”

Participants were focused on three areas – performance, endurance and price. Many experts are calling for standardization of SSD performance metrics to eliminate the current state of confusion over SSD performance metrics. That would help avoid the “benchmarketing” we are often forced to suffer in this industry.

When I mentioned the NAND flash endurance debates of the past, I was alluding to the MLC versus SLC wars that have been waged over the years (often with Toshiba and Samsung as the respective combatants). The key information returned from the Summit was based on a usage model of 20GB per day for the typical consumer. This means that MLC NAND flash could provide sufficient lifetimes for consumer SSD products.

Several summit participants tried to predict the future of the SSD market by comparing it to the HDD market of long ago. Expect some major rounds of consolidation considering that there are more than 70 SSD manufacturers today.

But it seems like there is more driving SSD technology than simple bits and drive endurance. There is a shade of green overtaking the SSD conversation. Yes, saving energy and “going green” is a big part of the talk about SSD’s. At the Summit, the local California utility, PG&E, promoted the need to reduce energy demands through technological innovation. Their example was the power consumed by large data centers which can be reduced by transitioning to SSD.

Young mentioned that Intel will have some interesting things to discuss at the Intel Developer Forum August 19 through 21. Intel may concentrate on the controller for SSD, and this may actually be the key component to making NAND work in the SSD. The way operating systems use the hard disk is really tough on flash. For robust SSD’s in our future laptops, we will be relying on Intel and others to implement intelligent control and management of which physical memory locations are used to even out the wear over the whole flash chip over the life of the product. SanDisk has proposed their own version that they are calling LDE or Long Term Data Endurance.

I am in London this week and just wrapped things up at the Intertech-Pira Image Sensor Conference. It was an interesting event with a diverse programme. There was everything from cameraphones to disposable endoscopes to swarms of robotic surveillance insects. Wait. The bugs were just my own nutty comment lifted from IEEE Spectrum. After a day where a single conference session dealt with both cameraphones and tiny cameras placed on the ends of laproscopic surgical instruments, Technology Review was very timely with their news of a cameraphone microscope.

But there was more to the conference than pictures of internal organs (right before lunch, thank you) and discussions of better ways of yanking gall bladders out through small pipes stuck into people.

What was hot? Well HDR – or high dynamic range – was. However, the definition of HDR was nowhere near consensus. HDR capability will be required in both security cameras as well as forward looking driver assistance cameras for cars. The other technology worth watching is backside illuminated imagers. Although it was not a featured topic in a session or even a single paper, it did pop up again in a few interesting places. I got turned onto the backside idea for the first time at IISW last May. Although it was introduced to me relatively recently, it’s been under investigation for a long time. Now it seems like it is picking up some momentum inside image sensor companies and starting to be considered for a potential production technology.

Sensors were not the only interesting discussion. Day two offered everything from the use of Flickr in image enhancement algorithms to shape memory alloys.

Graham Townsend, founder of Spiral Gateway, presented an interesting alternative to ASIC-based  Image Signal Processors (ISP). His team’s “soft” ISP approach avoids the 12 to 18 months lead time to get image processing algorithms hardwired into silicon. The obvious advantage is that the latest algorithms developed can be used in the cameraphone right as it goes into production, and they can be changed even after product launch simply by compiling new C code. Their chip is only slightly larger than a full custom ASIC providing the same processing (16 versus 14 square millimetres including I/O). The idea is based on RICA or re-configurable instruction cell array. Although I know virtually nothing about this architecture or other microprocessor alternatives, I would say the ISP application is only the tip of the iceberg. I can only explain it by borrowing one of Graham’s bullet points - ASIC netlists, wired up ‘on-demand’ in real time. (By the way, the iceberg analogy is quiteappropriate considering that co-chair, Lindsay Grant introduced Townsend by saying that Graham often referred to CMOS image sensors and imaging 10 years ago as just the tip of another iceberg.)

The shape memory alloys are being used by a company called 1…Limited to move the lens in an autofocus system. The alloy wire takes up almost no space (diameter is only 25 microns) inside the module providing space for larger lenses inside smaller modules. The next application of their wire is for adding zoom to future cameraphones.

Professor Raimondo Schettini from the University of Milano (Bicocca) gave an intriguing lecture on image enhancement techniques. These are more than the simple enhancements like automatic face detection or red-eye reduction that are so well known. His group has developed several algorithms for improving images based on decision trees to determine if the image is indoor or outdoor and so on to select the best algorithm based on determining the context in which the photograph was captured. A very interesting extension of that idea was the use of the web and the growing set of not only posted images but also user comments. This is visionary stuff. And I’m not just saying that because  my own presentation suggested that Google Street View might create the next image sensor boom! Professor Schettini intends to use the vast database available on Flickr to selectively apply algorithms to improve the image quality. As one slide pointed out, this is truly “data mining on all the available data.”
 
After IISW last May, this was my second chance to attend a relatively small meeting of image sensor technologists (and marketers as the case was this week). What I have discovered is that image sensor experts are not only extremely talented in their various fields but also a distinctly fun and classy group of people. I think there is a unique level of understanding within the imaging community that each sub-specialty represents only one part of a complex system that creates a final image and that all of the system components in delivering the final product are equally important.

Now an anecdote…I have a long and strange history of people getting my name wrong. I thought “Don” was pretty simple. I don’t know why, but the telephone company has listed me more than once as “Dan.” People I’ve met even several times often prefer “Dan” as well, but I thought everything would be okay here in London. I hoped I would come to a conference with my name correctly indicated in the programme (it was), give out some business cards with my name spelled properly (it was), and show a title slide with my name shown clearly as “Don,” and people would get it right. But I guess my parents were the ones who got it wrong. Within about 90 minutes of presenting yesterday, I was sitting at the same lunch table as an attendee who referred to me as “Dan the Insights guy.” I hope it doesn’t stick.

That’s all for Dan from London. (Well, if you can’t beat ‘em…)

Okay, so this post is a day after the news, but that’s still better than posting beforehand to create the appearance of a scoop. Yesterday, Intel’s much anticipated presentation of their 45nm process was held at IEDM in Washington. Although I suggested last week that Intel would reveal certain details of their process, much of it still remains a mystery to the wider public. Of course, the devices are openly available allowing one to actually see what’s inside. The IEDM paper gives many details about staying on the curve (Moore’s Law, that is) and the transistor performance the 45nm HKMG process achieves. But it’s more than a little short on details of how that performance is enabled. Anyone fortunate enough to analyze one of the Penryn chips could even conclude that Intel was hoping to throw us all off the scent. (I apologize too since my Perler bead model in the photo is also a bit misleading.)

Intel describes the transistor formation as “high-k first and metal gate last.” If last means after sacrificial poly, then that description is not entirely accurate.

But IEDM offers more than the Intel 45nm show. This was even evident even to Popular Mechanics’ blogger who noted that Intel 45nm would be “duelling” with the AMD, IBM, Freescale, Sony and Toshiba announcement about 32nm. I appreciate, though, the fact that neither the “duel” or Intel’s 45nm presentation itself obscured some more futuristic technology for at least this one reporter in DC. Check Popular Mechanics for some pictures and description of Stanford and Bosch spiral sensor arrays and the University of Tokyo “communications sheet” that allows devices placed on it to communicate with one another while receiving power for charging (also on TR today.

As an IEDM outsider this year, I picked the energy harvesting devices session (14) as a must see. Running parallel to the CMOS technology platform session, I’m sure that it was largely overshadowed by the big boys. But many of these concepts will benefit humankind in a variety of ways and arguably more than CMOS IC technology. As most will guess, the harvesting session includes photovoltaics or solar cell technology, one of the hottest and most newsworthy topics of the last year in the semiconductor industry.

Everybody knows about oil crises, global warming and the Kyoto protocol, so alternate energy is really a topic for the mainstream news channels. But micro- and nano-power generation is where it’s at. Or I guess I should say where it will be at. Check some earlier posts to SemiSerious to track down some information in this exciting field. I really think this will be field that enables many amazing devices from multipurpose nanobots in your bloodstream to wide area sensor nets keeping tabs on the population for the large sibling.

At the Common Platform Technology Forum last month, the design for manufacturing (DFM) session message was, “not if but when the industry will have to move to structured gate layouts.” Intel already has.

The industry is at a point where design for variability (DFV) is required. The old approach would be to add margin, but design margining has no scalability and no future.

A better option is to take a DFM approach that creates more litho-friendly designs. Intel has pushed out investment in new lithography tools, keeping their 193nm dry toolset at 45nm. Surely, one outcome of that decision was a requirement to use restricted design rules or a “structured” gate layout to improve yields. There is tangible evidence of this on the Penryn die. The metal gate lines are patterned in regular, parallel patterns to improve both printability and processing to maintain fidelity of the final structures. CMP is obviously a critical step in Intel’s gate last approach, and the structured layout also improves CMP. Filling the narrow trenches with the metal gate material must be easier too when there are fewer nooks and crannies in nice straight gate lines.

In an effort to maintain control of the message as information begins to leak out just before their IEDM presentation on Tuesday, Intel’s Kaizad Mistry provided a few nuggets to Semiconductor International. By restricting design rules to keep poly lines running in a single direction and switching to a wider SRAM architecture, Intel was able to push its SRAM feature size harder, Mistry said, adding that, “Many times, these design changes are beneficial for patterning.”Semiconductor International reports that Intel used double patterning lithography to “square off the ends of the patterns, reducing rounded ends (dogboning) and irregular shapes (icicles).” Looking at the Penryn deprocessed to tungsten metal 1, it is easy to compare the double-patterning used at the metal level to the tungsten trenches where it was not. According to Mistry, “There are benefits in terms of performance and layout density. The trench contact serves as a form of what you might say is local interconnect. And in terms of patterning, it is easier to pattern lines and spaces than a field of holes.”

I’m sure it’s not intentional, but the PMOS image released by Intel is a little misleading. At their paper on Tuesday at IEDM, look for Intel to clarify the situation by showing that the real story of their metal gate is much closer to the hafnium oxide high-k layer.

While attending the IBM and associates Common Technology Platform Forum this afternoon, it occured to me that I was bridging the gap between the design community and trying to get it right, and the failure analysis community that steps in too often to mention in polite company. That’s because I am also in San Jose to attend the International Symposium on Testing and Failure Analysis (ISTFA). The gap is more than a conceptual one as well since there are few if any slick executives at ISTFA. In fact, “engineer” is a word that is spoken in a somewhat unflattering fashion by many ISTFA presenters. But I refuse to hide my iron ring. (Big deal, I know since Canadians are in short supply at these events. Maybe at tonight’s Sharks game, it would be recognized but SI still hasn’t heeded requests to include pro-sports packages into corporate travel arrangements.) Since so many failure analysts are engineers, I guess it’s really designers – not engineers at large – that are the brunt of this abuse.

Intel Fellow Dr. Mario Paniccia enlightened the crowd with Silicon Photonics: Opportunity, Challenges & Applications. Dr. Paniccia is director of the photonics technology lab, but he got his start in quality and reliability at Intel. In fact, this appears to be how Intel decided that optical components on silicon made sense. It was the success of optical fault isolation and analysis tools used in silicon FA that got them thinking. If electro-optical interactions in silicon could be exploited for detecting failures, why not find a way to make photonic devices?

Without going into too much detail (I would not do it justice anyway), waveguides can be built very effectively on SOI. The game-changer for photonics is that silicon has patterning and processing tools available that are leagues ahead of the III-V equipment. As Dr. Paniccia said, the silicon photonics world can “draft” two or three generations behind Moore’s Law and still produce components that are beyond the wildest dreams of traditional photonics providers in terms of booth footprint and cost.

The trick to making this work is to get lasers and detectors onto silicon. Since silicon is an indirect bandgap material, emitters and detectors are better left to the compound semiconductors. But that is not a real set-back to the silicon developers because complicated packaging and assembly is still required of non-silicon components. Intel has developed ways to align multiple InP-based lasers onto their silicon waveguides at the wafer level. This work, done in collaboration with the University of Santa Barbara, has developed 30+ 40Gb/s parallel tranceivers. Get some more details from the Intel blog.

At this time, I would like to pass along my condolences to the III-V photonics community. With the Intel powerhouse on the verge of making your optical components as dirt cheap and tiny as today’s DRAM and flash, I believe your days are numbered.