SemiSerious

I am in London this week and just wrapped things up at the Intertech-Pira Image Sensor Conference. It was an interesting event with a diverse programme. There was everything from cameraphones to disposable endoscopes to swarms of robotic surveillance insects. Wait. The bugs were just my own nutty comment lifted from IEEE Spectrum. After a day where a single conference session dealt with both cameraphones and tiny cameras placed on the ends of laproscopic surgical instruments, Technology Review was very timely with their news of a cameraphone microscope.

But there was more to the conference than pictures of internal organs (right before lunch, thank you) and discussions of better ways of yanking gall bladders out through small pipes stuck into people.

What was hot? Well HDR - or high dynamic range - was. However, the definition of HDR was nowhere near consensus. HDR capability will be required in both security cameras as well as forward looking driver assistance cameras for cars. The other technology worth watching is backside illuminated imagers. Although it was not a featured topic in a session or even a single paper, it did pop up again in a few interesting places. I got turned onto the backside idea for the first time at IISW last May. Although it was introduced to me relatively recently, it’s been under investigation for a long time. Now it seems like it is picking up some momentum inside image sensor companies and starting to be considered for a potential production technology.

Sensors were not the only interesting discussion. Day two offered everything from the use of Flickr in image enhancement algorithms to shape memory alloys.

Graham Townsend, founder of Spiral Gateway, presented an interesting alternative to ASIC-based  Image Signal Processors (ISP). His team’s “soft” ISP approach avoids the 12 to 18 months lead time to get image processing algorithms hardwired into silicon. The obvious advantage is that the latest algorithms developed can be used in the cameraphone right as it goes into production, and they can be changed even after product launch simply by compiling new C code. Their chip is only slightly larger than a full custom ASIC providing the same processing (16 versus 14 square millimetres including I/O). The idea is based on RICA or re-configurable instruction cell array. Although I know virtually nothing about this architecture or other microprocessor alternatives, I would say the ISP application is only the tip of the iceberg. I can only explain it by borrowing one of Graham’s bullet points - ASIC netlists, wired up ‘on-demand’ in real time. (By the way, the iceberg analogy is quiteappropriate considering that co-chair, Lindsay Grant introduced Townsend by saying that Graham often referred to CMOS image sensors and imaging 10 years ago as just the tip of another iceberg.)

The shape memory alloys are being used by a company called 1…Limited to move the lens in an autofocus system. The alloy wire takes up almost no space (diameter is only 25 microns) inside the module providing space for larger lenses inside smaller modules. The next application of their wire is for adding zoom to future cameraphones.

Professor Raimondo Schettini from the University of Milano (Bicocca) gave an intriguing lecture on image enhancement techniques. These are more than the simple enhancements like automatic face detection or red-eye reduction that are so well known. His group has developed several algorithms for improving images based on decision trees to determine if the image is indoor or outdoor and so on to select the best algorithm based on determining the context in which the photograph was captured. A very interesting extension of that idea was the use of the web and the growing set of not only posted images but also user comments. This is visionary stuff. And I’m not just saying that because  my own presentation suggested that Google Street View might create the next image sensor boom! Professor Schettini intends to use the vast database available on Flickr to selectively apply algorithms to improve the image quality. As one slide pointed out, this is truly “data mining on all the available data.”
 
After IISW last May, this was my second chance to attend a relatively small meeting of image sensor technologists (and marketers as the case was this week). What I have discovered is that image sensor experts are not only extremely talented in their various fields but also a distinctly fun and classy group of people. I think there is a unique level of understanding within the imaging community that each sub-specialty represents only one part of a complex system that creates a final image and that all of the system components in delivering the final product are equally important.

Now an anecdote…I have a long and strange history of people getting my name wrong. I thought “Don” was pretty simple. I don’t know why, but the telephone company has listed me more than once as “Dan.” People I’ve met even several times often prefer “Dan” as well, but I thought everything would be okay here in London. I hoped I would come to a conference with my name correctly indicated in the programme (it was), give out some business cards with my name spelled properly (it was), and show a title slide with my name shown clearly as “Don,” and people would get it right. But I guess my parents were the ones who got it wrong. Within about 90 minutes of presenting yesterday, I was sitting at the same lunch table as an attendee who referred to me as “Dan the Insights guy.” I hope it doesn’t stick.

That’s all for Dan from London. (Well, if you can’t beat ‘em…)

Yesterday marked the dawn of a new era of scaling for CMOS devices. I hope that statement fits with all the hype around the launch of the 45nm microprocessor from Intel. In fairness, though, switching to metal gates and high-k dielectrics represents an important milestone in semiconductor technology. Gordon Moore’s well-worn comments are appropriate:

“The implementation of high-k and metal materials marks the biggest change in transistor technology since the introduction of polysilicon gate MOS transistors in the late 1960s.”

Intel released TEM images of its 45nm PMOS transistor. The embedded SiGe source / drains are evident, but we’ve all seen those before. For his keynote, Paul Otellini seemed confident that we could not tell what Intel’s secret sauce in the dielectric and workfunction metals was, but they had something to hide on top of the gate stack. We can’t see the CMP surface, but that’s a no-brainer for a replacement gate (aka gate last) technique. I think they want to keep the capping material on top of the gate electrode hidden until they present at IEDM (Paper 10.2). At about 9:30 on the morning of December 11 in Washington, DC, Kaizad Mistry will open the trench coat on the 45nm HKMG process. Considering the secrecy Intel has been able to maintain on this process, I think the trench coat is a fair reference. Intel deserves full marks for keeping its employees and vendors quiet for so long. Steve Jobs is jealous, I’m sure.

Or maybe he’s not. SI will be opening the kimono on the Penryn this Friday to all our clients participating in the analysis. Intel will still generate lots of excitement at IEDM (at least if you aren’t analyzing 45nm or buying one of our reports).

There’s been much hype and there will be much more.  The Penryn MPU hit Time magazine’s list of best inventions of 2007 along with the iPhone cover girl. Intel may covet the iPhone socket and may well win it for next generation devices, but there may could be another connection to Time’s list. NASA’s methane powered rocket might one day look to the Intel marketing machine as a steady source of fuel.

While attending the IBM and associates Common Technology Platform Forum this afternoon, it occured to me that I was bridging the gap between the design community and trying to get it right, and the failure analysis community that steps in too often to mention in polite company. That’s because I am also in San Jose to attend the International Symposium on Testing and Failure Analysis (ISTFA). The gap is more than a conceptual one as well since there are few if any slick executives at ISTFA. In fact, “engineer” is a word that is spoken in a somewhat unflattering fashion by many ISTFA presenters. But I refuse to hide my iron ring. (Big deal, I know since Canadians are in short supply at these events. Maybe at tonight’s Sharks game, it would be recognized but SI still hasn’t heeded requests to include pro-sports packages into corporate travel arrangements.) Since so many failure analysts are engineers, I guess it’s really designers - not engineers at large - that are the brunt of this abuse.

Intel Fellow Dr. Mario Paniccia enlightened the crowd with Silicon Photonics: Opportunity, Challenges & Applications. Dr. Paniccia is director of the photonics technology lab, but he got his start in quality and reliability at Intel. In fact, this appears to be how Intel decided that optical components on silicon made sense. It was the success of optical fault isolation and analysis tools used in silicon FA that got them thinking. If electro-optical interactions in silicon could be exploited for detecting failures, why not find a way to make photonic devices?

Without going into too much detail (I would not do it justice anyway), waveguides can be built very effectively on SOI. The game-changer for photonics is that silicon has patterning and processing tools available that are leagues ahead of the III-V equipment. As Dr. Paniccia said, the silicon photonics world can “draft” two or three generations behind Moore’s Law and still produce components that are beyond the wildest dreams of traditional photonics providers in terms of booth footprint and cost.

The trick to making this work is to get lasers and detectors onto silicon. Since silicon is an indirect bandgap material, emitters and detectors are better left to the compound semiconductors. But that is not a real set-back to the silicon developers because complicated packaging and assembly is still required of non-silicon components. Intel has developed ways to align multiple InP-based lasers onto their silicon waveguides at the wafer level. This work, done in collaboration with the University of Santa Barbara, has developed 30+ 40Gb/s parallel tranceivers. Get some more details from the Intel blog.

At this time, I would like to pass along my condolences to the III-V photonics community. With the Intel powerhouse on the verge of making your optical components as dirt cheap and tiny as today’s DRAM and flash, I believe your days are numbered.

The new buzz word - acronym actually - coming out of today’s IBM-Chartered-Samsung Common Platform Forum today here in Santa Clara is the term introduced by Qualcomm Senior VP and GM, Behrooz Abdi. His view of the consortium is to create an “integrated fabless manufacturer” or IFM akin to the IDM he means to displace. (Qualcomm has after all surpassed TI in the RF space perhaps leading TI towards its fab-lite ideas.)

IBM and its partners here are putting on a great show. Lunch is over now, and it’s time to get back to the sessions, but I will post more later. Unfortunately, that will be after things shut down back East.

Trying to mute the old joke that compound semiconductors are the technology of the future and always will be, Dr. Vu Ho recently attended the 2007 International Conference on Compound Semiconductor Manufacturing Technology. The III-V compounds and related materials such as GaAs, GaN and InP have for years been a mainstay of advanced platforms in military and aerospace applications. However, they have not penetrated deeply into the high volume consumer segment that gets executives and investors salivating.

The higher performance offered by the “un-silicon” materials have been well known for many years. Higher carrier mobilities and semi-insulating substrates enable transistors and circuits to operate at higher frequencies and with lower losses (see more details here). For many years, the competition for maximum operating frequencies - f_T and f_MAX - put III-V’s well ahead and kept silicon devices out of the running. In the lucrative cell phone portion of the radio frequency market, compound devices established and maintained a foothold. Those components are all related to the RF front-end. Duplexer filters, switches, output power amplifiers, and receiver amplifiers (LNA’s) were all once III-V based. The first erosion of this share was still a compound, but still silicon-based, as silicon-germanium - SiGe - grabbed a piece of the power amplifier market.

Unfortunately for the III-V community, the huge momentum and power of the silicon world continued to push into this space. In the quest for becoming all-digital, today even low-power stages of the RF path are in digital CMOS. There is even an RF switch in Si - albeit on sapphire. In fact, aggressive scaling CMOS transistor dimensions has driven the speed performance to near III-V levels with all competitors reaching hundreds of gigahertz.

Despite the switching speed, transistor density, and relative ease of integrating many functions in one technology platform, CMOS may not win out. Dr. Ho points out that the breakdown voltage and power handling limitations of silicon devices (including SiGe) will limit their march to higher operating frequencies. According to Dr. Ho, the future of III-V devices looks bright.

Power up.

A couple of weeks ago, my good friend and semiconductor analysis colleague, Mark Chambers, attended the IITC in San Francisco. The sessions were held from June 4 to 6 at the Hyatt Regency at San Francisco Airport. Because the dates spanned my wedding anniversary and wife’s birthday and the conference site was far from downtown, I could not attend and Mark has promised not to engage in any “San Francisco” humour.

I talked to Mark about the IITC, and he provided me the following thoughtful and insightful comments.

DS: So Mark, do you have any comments about the conference beyond what I just read at Semiconductor International?

MC: You know how you can witness an event, spend a little time digesting it, then read an article about it and wonder if you were at the same event as the author of the article?

DS: I have the same experience if I watch an entire hockey game on TV and then see the highlights on the sports news.

MC: This article suggests that the “popular” issue of the day was 3-D integration. There were a number of interesting papers presented on the topic, including one from IBM where they mounted SRAM over an 80 core processor and made direct connection to a specific core. LETI presented, as they did last year, their scheme for 3D which uses copper “nails” which is really a variation on the through silicon via (TSV also refferred to as ISV in the article hyperlinked above), although with different processing steps.

But I don’t feel it was any more popular than other themes in the conference. In fact I would have thought there was more attention paid to the papers on low-k including the reliability issues (because there are many).

Dan Edelstein - the manager of the department that made the press release about IBM’s air gap - made a presentation that was broad in the technologies covered, but would only reveal the same info that was in the press release. A paper on IBM’s air gap will be presented at the Advanced Metallization Conference in October. Dan Edelstein will also be giving a tutorial session at that conference.

As a general comment, the papers presented this year seemed like a bit of rehash of last year, with some refinements thrown in. I sense a growing cynicism about whether we’ll see an integrated low-k in production that is less than 2.2 (obviously there is skepticism about IBM’s air/vacuum as a viable dielectric) . Overall, I was fascinated by most of the papers presented as they focused in on the practical issues of following the ITRS. I got the impression that there was no further discussion about the longevity of Moore’s Law, rather, there was a lot of imagination about what happens after its collapse. Only 2 papers on CNTs appeared this year.

DS: What was the attendance like? 

MC: I don’t have actuals but I think there were more there than last year. I’m guessing closer to 1000 which would put it at its highest attendance ever. 

DS: What type of attendees were most in evidence - students, engineers, management etc?

MC: The majority were engineering types by my guesstimates with some management and most of the posters by grad students.

DS: Were most of the attendees North American, or what guesstimate would you make of the breakdown - Asia, US, Europe?

MC: There was a strong representation from the Pacific Rim and Europe, combined probably 50%, the remainder from North America.   When I think about it China (unless you include TSMC and UMC) was conspicuously absent, at least from the list of presenters anyways. 

DS: What was the buzz?

MC: IBM’s press release on AGE (air gap exclusion) was obviously on a lot of people’s minds due to the integrity issues associated with it, but everyone from IBM was obviously told to stay mum on the subject. I had lunch with one of the team members and couldn’t pry anything out of him (discreetly, of course).Other papers on AGE included the traditional pinch off method with CVD but there was a really interesting method presented by NXP/Dow that included the use of a thermally degradable dielectric to produce voids that, if it worked as claimed, circumvented the IBM problem with mis-aligned vias.

DS: What technology seemed to attract the most attention?

MC: Not an easy question to answer. In general the audience was unemotional (refer to earlier comments on attendance). Many papers only got questions because of the long pause waiting for questions. Wafer to wafer integration (or chip to chip) seems to be emerging as a given. One paper suggested it was no longer an innovation but rather an evolution.

DS: What sessions did you attend?

MC: All presentations were in series. I went to all of them.

DS: Good answer in case your manager reads this. Which was the most interesting session?

MC: I’m fascinated by the idea of AGE. It’s interesting to watch the various approaches taken to its integration - nothing has been presented that includes data on reliability after CMP or packaging. Throw 3D on top of that (literally) and it will be interesting to see if it makes it to production. There were only 3 papers on it this year and IBM seems to be the furthest along in development (at least, according to the press). I’m aware that AGE is an old technology in some ways but so much has changed since it’s inclusion in devices from years ago. The thermally degrading dielectric looks interesting. 

Dan Edelstein made the IBM presentation that touched on AGE and was quite communicative (except with reference to AGE).

DS: What seemed to be the most popular session?

MC: I don’t recall a most popular.

DS: Hmmm… Okay, so what papers attracted the most questions?

MC: When Dan Edelstein presented his paper on advanced Cu metallization, he was able to stickhandle like Sid the Kid (DS - if you don’t get the hockey reference please link here) to avoid those referring to AGE. There were lots of questions on the thermally degrading dielectric as well.

DS: Which companies attendees seemed to be asking the most questions? 

MC: There were 3 people who were consistently asking questions, and the cynic in me thought that it was merely an attempt to get air time for themselves or their company.

DS: What technology was the hottest in terms of the number of papers?

MC: At a first glance, I would say that there were roughly an equal number of presentations surrounding 3 topics:

• lowering k in dielectrics,
• decreasing R in the metal lines and the last,
• how the first two affect reliability

DS: What company was the most prolific at the conference?

MC: I would say it’s between IMEC, Crolles2 Alliance (STM)  and Freescale. 

DS: Mark, that was great. Thanks for your time, but most of all, thank you for your analysis. You really cut through a lot of the bull that someone attending the event might have to suffer. 

With the VLSI Syymposia just a little over a month away, I will wrap up my picks for papers to watch for by looking at DRAM. For the Technology Symposium, Samsung is over-represented with five out of the seven presentations split between two sessions.

Two of Samsung’s articles will discuss aspects of their FinFET DRAM cell, touted as the enabler for sub-50nm devices. The second paper appears to provide more details of the process and cell performance. If enough details are provided at the conference, it could be enough to predict Samsung as the first to make it to production with a FinFET device.

Qimonda is the only other vendor presenting a technology paper. In their forward-looking work, carbon is proposed as a new capacitor electrode material for DRAM. The technology includes a high-K dielectric for the trench capacitor, so Qimonda moves to carbon-based materials for better thermal stability. Qimonda’s other paper promotes trench technology beyond 40nm with a discussion of an array transistor that is self-aligned to the trench.

But the best paper for insight into production technology is provided in the final DRAM paper. Samsung announces it’s 56nm, 1Gb technology patterned on an ArF immersion tool. A 0.19 square micron cell size is reported. To achieve this scaled cell, Samsung moves to an elevated source / drain structure for the first time. Micron has used a similar structure for a few generations now. The capacitor dielectric is “ZAZ” which is a sandwich of zirconium and aluminum oxides for increased K value. Based on some work shown by Kinam Kim at IEDM 2005, I expect that the higher aspect ration capacitors at 56nm could use the Samsung “MESH-CAP” design for mechanical stability.

In yet another article, Samsung talks about hafnium dielectrics for DRAM. Of course, we have already seen this used in capacitors, but this work describes hafnium in a HfSiON dielectric for the access transistor.

Samsung is the DRAM dominator, and they lead this conference along with many others in presenting their technology developments. Unfortunately, I will not have a chance to see any of these papers first hand, but my good friend and colleague, Ramesh Kuchibatla will be in Kyoto and provide both scoops and scams he discovers at the event.

This is my second review of papers to be presented at the VLSI Technology Symposium. Today, I will take a look at the most promising papers on phase change memory technology (PCM or PRAM). Today at its spring development forum in Beijing, Intel announced that it will produce a 128M 90nm PRAM later this year. This is bound to create some extra buzz around the many good PRAM papers to look forward to at VLSI.

Samsung dominates the PRAM submissions as you might expect from some of their announcements in the past year. They will present a phase change cell based on GeSbTe for sub-50nm generations that appears to keep reset current below 260µA.  PRAM designs typically suffer from high currents required to heat and change the phase of the active layers. In another paper, Samsung memory engineers plan to present a novel heat dissipating cell scheme to improve the reset characteristics across a large (512M) array.

Naturally, Intel does have a paper in the NVM category. Oddly, though, it is a traditional floating gate NOR. Intel’s flash team will present “A Scalable Self-Aligned Contact NOR Flash Technology.” Sounds a bit bland, but it promises technology for 40nm and beyond. At 65nm, the cell area is only 0.036 square microns which is a cell area factor improvement from 10.6 on their 65nm production technology down to 8.5. This team’s ability to push the floating gate NOR cell is somewhat at odds to the PRAM announcement that was billed - in the EETimes article anyway - as the replacement for the floating gate.

In a way, it makes sense for Intel to get PRAM into the market first. But you need to look back a few years before STMicroelectronics began to make big strides and invest a lot of energy in PRAM development. Intel was the first major player to invest in phase change memory by funding a spin-off from the creators of ovonics. Energy Conversion Devices was the corporate entity that grew out of the pioneering work of Stanford R. Ovshinsky in 1960. A separate company - Ovonyx - was formed in 1999 to commercialize the “Ovonic Unified Memory” or OUM. Today, OUM has a sexier name. PRAM is “perfect RAM” in the Samsung vernacular.

That’s enough of a history lesson though. It does sound as though we will have a chance for the Intel PRAM and NOR flash to go “head-to-head” soon albeit with PRAM making its mark using older generation litho tools.

Despite the talk of Intel mass production with Samsung and STMicro doubtless charging hard, an IBM paper may have the most interesting new technology to present. Details are sketchy to non-existent at this point regarding, “Novel Lithography-Independent Pore Phase change Memory.” It certainly sounds like the first NVM session will be worth attending to hear about this work along with Samsung’s.

Once again last week, the organizers of the VLSI Technology and Circuit Symposia organizers supplied me with this year’s abstracts and conference summary. As always, there are a lot of great papers with all geographic regions well-represented. For today’s blog, I will start a series of posts about which papers and technologies to watch for June 12 to 14 in Kyoto.

45nm and high-K metal gate have been the hot topics ever since Intel and IBM announced them for their respective high performance CMOS logic platforms, so I will start with 45nm logic today. There are many interesting papers planned for VLSI Tech related to technologies for 45nm logic. IBM and IMEC are the best represented organizations. There are no Intel logic papers at all. You can find out about Intel 45nm from a platform perspective with some awesome videos from Scoble at PodTechNews. This video is the edited celebration of Intel’s success driving Moore’s Law. You can also get the “fab” tour from Mark Bohr, the device testing lab, Kaizad Mistry in the bunny suit, and the whole 45nm MPU line-up. Back to VLSI, there are a smattering of contributions from AMD, Fujitsu, NEC, Renesas and Toshiba as well.

The highlight session will feature one IBM presentation that is bound to generate interest. “High Performance Transistors Featured in an Aggressively Scaled 45nm Bulk CMOS technology” describes an allegedly world-leading drive current performance of 1150µA/µm for NFET and 785µA/µm for PFET. Just as an aside, I should point out that a Samsung paper promises 1620µA/µm for NFET. It is interesting to me that IBM is describing a bulk rather than SOI technology for 45nm. IBM has produced SOI IC’s at both 130 and 90nm. The interconnect scheme features ultra low-K of 2.4. The gate material is not mentioned.

In fact, there are no IBM papers that mention the gate material. Many other presenters will, however. That list includes IMEC, National university of Singapore, and Samsung. The commonality among these is that they will all discuss various flavors of FUSI or fully-silicided poly as opposed to metal gate structures. It would appear that the FUSI concept is not only alive and well but has a large following in the industry.

The theme of this trip for me was, “I get by with a little help from my friends.” Upon arriving in San Francisco, I found myself in a taxi bound for the conference hotel without my wallet and barely enough cash for the fare. Fortunately, two of my SI process analysis colleagues were already there, and they were gracious (and trusting) enough to put my room on their own credit card. Problem solved.

As always, Sunday is a training day. Two tracks were offered, and I chose the “Memory Technologies for 45nm and beyond.” This offered some interesting material. There were excellent sections on SRAM (Harold Pilo, IBM), DRAM (Howard Kirsch, Micron), and emerging NVM (Agostino Pirovano, STMicroelectronics). In my experience, STMicro presentations at these events are always excellent. This was another thorough and objective summary of a hot topic area. Anyone getting started in understanding current and future trends for non-volatile memory should start with this presentation.

Monday morning began with presentation of the yearly Electron Device Society Awards along with three plenary talks. C.G. Hwang?s from Samsung gave an especially entertaining lecture, “New Paradigms in Silicon Industry, Business, and Technology.” How could anyone doubt that Samsung will be the industry?s number one some day after listening to this speech?

The Monday reception offers an excellent chance to meet old friends and establish new contacts in the main brain trust of the semiconductor technology. My evening was abbreviated however. It was only a quick hello to Scott Jones, our ICKnowledge partner, and a quick good-bye for me. My farewell also turned out to be quite final (in terms of the conference). My early departure from the reception on Monday night was driven by a horrible intestinal bug. I dared not leave my hotel room for the rest of the conference.

And that?s where my friends came to my aid again. Ramesh and Moira kept tabs on me the rest of the time to make sure I was still alive. Between the drugs and a half-gallon Pedialyte supplied by Moira, I was able to re-hydrate myself and establish sufficient electrolyte levels for the long flight home Wednesday night.

I hope to be a more active participant next year, but until then, I will post more summary and opinion of the technical content from this year?s IEDM. For this too, I will need a lot of help from my friends.