SemiSerious

Last week I attempted to preview the upcoming VLSI Symposia. The conferences are in Japan this year, and my attention was quickly diverted to the current situation in the Japanese semiconductor industry. With all that off my chest, I am free this week to actually look at some of the papers that will be presented starting June 15 in Kyoto.

Maybe it’s because our industry and the whole economy is in the dumps and consolidation is on everyone’s mind or maybe I just didn’t pay much attention before. Either way, looking through the advance program’s list of authors, I was struck by what I thought were some unlikely collaborators.

Of course, there are the teams of researchers that you expect from the well known business partnerships. There is a joint AMD/IBM paper in the Special Technology Highlights Session on Tuesday. T7-2 is devoted to high-K, metal gate integration for 22nm “and beyond.” The full title gives a nice bump to the word count for this blog:

“Extremely Scaled Gate-First High-k/Metal Gate Stack with EOT of 0.55 nm Using Novel Interfacial Layer Scavenging Techniques for 22nm Technology Node and Beyond”

(I’m hoping these extra words count toward the practice I need to hit whatever the magic number is for writing that’s equivalent to the 10,000 hour principle described by Gladwell in Outliers.)

On the heels of this presentation is another collaborative work from AMD/IBM this time with the addition of Freescale. The title of T7-3 is more compact, but the long list of authors could really help if I was getting paid by the word. (Okay, I know what you’re thinking. If I’m getting paid for this, more than just blog readers are getting ripped off.) If all the contributors attend the session, there might not be room for you, but if not, it’s worth checking out.

The most interesting group of authors from AMD, IBM (TJ Watson Research), and Intel presenting research on a replacement technology for CMOS. It’s pretty academic and includes UCLA and University of Notre Dame participants, but it’s interesting that it’s not a Sematech activity which is where such an unlikely group of allies might be more expected. You could say it was just odd timing to discover this one since it was about the first time I read AMD and Intel in the same sentence after hearing about the EU ruling against Intel that may carry a fine of up to $1.4B if actually imposed. The EU’s fine was, after all, the result of some intense lobbying by AMD to governments in many regions to pay attention to what they claimed were monopolistic business practices. When they get together now, I wonder if these guys talk more about replacements for CMOS or what other jurisdictions might jump on the bandwagon against Intel now that the EU has taken the lead. For my part, I just wonder what happens to that money after it’s collected. Somehow, I doubt it will be used to drive innovation at AMD or anywhere else in order to improve the competitive landscape. I’m sure it will stimulate the economy though, at least for the restaurant industry (or wherever these bureaucrats rack up their expense accounts).

Getting away from politics for a second, the AMD-IBM-Intel paper is part of a special session 6B – “Beyond CMOS.” You could argue that such a session is hardly very special anymore since there have been so many. The larger question is the reason why so many of these panels, conference tracks, events, articles and webinars exist. Is it because judgement day for CMOS is really drawing near? Or is it just good marketing to leverage the fears of an industry with so much capital, manpower and training invested in CMOS technology?

Another presentation that caught my attention (and I wish I could attend) will be given by Samsung. My semiconductor analyst cronies and I have been wondering aloud how much scaling is left in Samsung’s landmark Spherical Recessed Array Transistor (S-RCAT) for DRAM. A change is expected soon since the S-RCAT appears to be approaching the limit at 56nm. Although technologists were impressed by this innovation from Samsung, the name RCAT was not all that exciting. Samsung PR folks are getting set to change that as they seem to be taking a more active role in naming their next technology. Samsung’s newest vertical DRAM cell transistor is going to be known as the TCAT – or Terabit Cell Array Transistor. “Terabit” is impressive sounding both in and outside technical circles. We live in a green age where the term climate change gave way to global warming which has recently been replaced by yet a newer brand name, perhaps tera or terra will manage to grab even more of the spotlight. And I shouldn’t leave out Canadian Football fans in Hamilton, Ontario. Samsung’s new DRAM transistor is bound to play well in TiCat country. (That last bit is included just for Steve Bitton, Industrial Control Design Lines editor at TechOnline and Hamilton TigerCat fanatic.)

In a related story (okay, I admit, that’s stretching things), CEA/LETI and STMicroelectronics will present a paper entitled, “GeOI and SOI 3D Monolithic Cell Integrations for High Density Applications.” If insulating substrates keep going (many don’t believe so) and germanium is adopted for the transistor channels (lots of important people believe this), then there is bound to be confusion down the road between “GeOI” chips and some future “GeoEye” satellite that is meant to track all of our movements. What if they need GeOI chips for the GeoEye satellite? That might be one FoxNews report worth watching.

For each of the jewels in the technology triple crown of conferences – IEDM, ISSCC, and VLSI – I hope to preview (and occasionally post-analyze) the papers. But what started as a quick look at the 2009 edition of the VLSI Circuits and Technology Symposia quickly veered into a commentary on the Japanese electronics industry.

This year, the conference site for the VLSI Circuits Symposium and the Technology Symposium is Kyoto, Japan. With the economy the way it is, we can expect a distinctly local flavor to these two events. The recession is the time to expect consolidation with some big mergers or acquisitions likely imminent. Semiconductor process development is getting so costly that it is definitely not for the faint of heart. (Is it only real men who own fabs?) Of course, partnerships are nothing new. The IBM fab club has been around for a long time through the Common Platform partnership. There is even some pre-competitive research going on through various entities like Sematech here in North America and SELETE in Japan. But I think things are moving beyond that. The most interesting news related to this was the Intel-TSMC announcement where Intel plans to move production of the mobile Atom processor to TSMC and eventually offer it as an IP core on the TSMC platform.

But Japan could be facing even bigger problems than what we see in North America or even Europe. It’s become casual to attach “unprecedented” to many things in the news, but round after round of big layoffs at several Japanese electronics giants is certainly that. Toshiba was one of the latest announcing 3,900 additional jobs eliminated adding to an earlier round where they shed 4,500 temporary workers. I’m not sure what Toshiba refers to as a temporary job, but perhaps it’s actually the term permanent position that needs more clarification these days. In any case, these measures appear quite drastic for conservative Japanese companies. Hopefully,  they have acted early enough and that nothing truly catastrophic faces the Japanese electronics industry.

Consolidation in Japan needs to happen now. NEC and Renesas appear set to merge. There is a possibility this will extend to include Panasonic as well since they were already engaged in some technology development with Renesas. Semiconductor Insights analysts have been deeply engaged for some time in preparing roadmaps to provide our technology outlook for the major players in the industry. The roadmap for Japanese semiconductor firms made me wonder how much technology development let alone IC volume manufacturing is in Japan’s future. All the big players appeared to be pushing hard into technology consortia like the IBM fab club or even partnering with TSMC like Fujitsu. Panasonic may be the last fab standing – at least for CMOS logic devices. If you think about it, that’s probably where Panasonic ranks considering they were the first manufacturer with a 45nm product on the market, beating even Intel.

Japan needs to continue to look beyond its borders and create global partnerships. Elpida is one company that has shown leadership in this area. To stay competitive with Samsung, Elpida moved to Taiwan through its partnership with Powerchip Semiconductor (PSC) back in 2003. If you want experience and expertise in huge volume manufacturing, Taiwan was and is the place to go. It was the only way to stay cost-competitive, and Elpida’s leadership realized that. Granted, a memory company needs to get that message earlier than a logic manufacturer given the commodity nature of memory, especially DRAM. Elpida continues to work hard on its manufacturing base in Taiwan with a 52% stake in Rexchip which seems to be the best positioned of the Taiwanese DRAM entities since the government’s plan to create the Taiwan Memory Corporation appears to be unravelling.

If 2003 was the year for a Japanese DRAM company to get into Taiwan, then 2009 may well be the year for a logic manufacturer to do the same. Right now, Fujitsu is considering its future on Formosa with TSMC. If they continue down that path, Fujitsu will be a survivor just like Elpida.

In the TechInsights tradition, every attempt is made to inspire those designers, engineers and builders who actually do the work of creating technology. To highlight this, a special awards ceremony was held recently in San Francisco. As many of you know, Semiconductor Insights has offered leading technology companies a chance to showcase their best efforts through the Insights Awards which have been handed out to deserving products for many years. As part of the larger TechInsights family, the SI Insight Awards are now presented along with the EETimes ACE Awards at the Embedded Systems Conference (ESC) organized by the TechInsights events team.

The Insight Awards is a year-long process whereby companies who feel their chips are worthy of recognition provide them to the Semiconductor Insights’ crack technology analysis team. After analyzing the performance, circuit architecture and manufacturing processes of the nominees, several sessions are held where the lead analysts present the case for the finalists in each category. The result of the intense analytical scrutiny and many heated debates is our list of winners for this year.

The Insight Award for Most Innovative DRAM technology was given to Micron for their 50nm 1Gb DDR2. If you want to learn more about this most advanced RAM, the best place to start is a great Carl Wintgens article on EETimes.

In a world dominated by iPods and portable media, the award for Most Innovative Non-Volatile Memory obviously holds special distinction (as well as well as contributing extra heat to the winners debates). This year’s very worthy recipient is Toshiba for their 43nm 16Gb NAND flash.

The third device category award in 2009 was presented for the Most Innovative Mobile Processor. The winner was Intel for the Atom processor. Who can argue? Intel devices power the lion’s share of netbooks, the hottest computing platform currently on the market. Not only that, but Intel is leading this charge with the most advanced logic process available today – its 45nm High-K metal gate technology.

And finally the award closest to my heart, for Most Innnovative Process Technology, went to IMFT for its 34nm, 32Gbit MLC, NAND Flash. Since this is an Intel-Micron JV, the Process Technology Award made it two each for both Intel and Micron. As SI’s GM, Emil Alexov pointed out at the ceremony, this is the first product beyond 40nm that we have analyzed. That’s quite a milestone, and it’s no surprise that it is was achieved through the collaboration of the likes of Intel and Micron.

For more a great roundup of ESC and the EETimes ACE Awards and the gala evening, your best bet is to go to see Junko Yoshida’s article on EETimes. The full list of winners is here and the photo gallery of the presentations is also available. The ACE presentations at ESC 09 included some special IEEE ACE honors as well. Please go to the excellent Spectrum Tech Talk blog to get their angle on the event.

So if you won for 2009, there’s no time to lose. Contact the awards coordinator (cystalc@semiconductor.com) to submit your best for 2010. If you didn’t win, our analysis team certainly did not minimize your accomplishments. There were many worthy finalists. Picking the winner was nothing close to easy. (If you read a previous post, you may have heard that it was a “long and sometimes arduous” process.) But if seeing your least favorite competitor receiving the championship trophy left a bad taste in your mouth, what better time is there to let us know why you deserve the crown in 2010?

This week marks the beginning of the long and sometimes arduous process of selecting winners in the SI Insight Awards in each of the technology categories. Of course, these are:

• Process Technology
• Non-volatile Memory
• DRAM
• Mobile Processor

Of course, it’s always a treat to talk to the creators of technology about their products. Sometimes, it’s more like listening to proud parents talk about their kids, but that isn’t always as painful as it sounds – unless you don’t like kids. Well, at SI we love the little offspring of all the different product groups out there. Dealing with the media relations, marketing groups and product managers means hearing lots about what sets each product apart from the competition. Ultimately, though, a seasoned group of Semiconductor Insights analysts will judge each entry on its significance to the industry as a whole.

The arduous part of this is sometimes comparing technologies that may not compete directly against each other in a product or technology space. Does the smallest feature size guarantee a Process Technology winner? Then, obviously, a memory device, or more likely, a flash memory device would always win. Maybe you have to discount the perfectly repetitive structure of the memory array and look at how dense the manufacturer packed in the logic gates. Alas, this would exclude a memory chip from winning since their digital circuits typically employ design rules miles behind both its own memory cells as well as leading edge pure logic devices like microprocessors.

Time to stop talking and start thinking about narrowing down the list of finalists in each of the categories. I certainly hope that this year’s Insight Awards inspire the creation of more leading edge devices (or at least their submission to our awards program) in 2009.

Considering this won’t go up until the third day of the conference, it just wouldn’t be right to call this “a preview.” However, last week, I had a chance to get just that from Mark Bohr as he provided an overview of Intel’s contribution to this year’s ISSCC program. Intel is very well-represented at the conference with a total of 15 papers including four of eight in the microprocessor session.

Although, I will not be attending the conference, I am receiving timely updates from our trio of engineers who are at ISSCC right now. Aaron Murray, James Bull, and Mohammad Ahmad are doing a great job of keeping everyone back here in Ottawa up-to-date on the happenings in San Francisco (at least the stuff that’s part of the official ISSCC agenda).

Mark Bohr’s plenary ended before I posted this, so there will soon be lots of places to find a digest of what he presented. The main point is that Intel is moving considerable effort into system-on-chip (SoC) development. As Mark showed, today’s microprocessors are actually really complex SoC devices incorporating several formerly discrete chipset components into a single IC. For example, the Core i7 – or Nehalem – design integrates the DRAM controller and DDR3 I/O’s. Intel is presenting more on Nehalem at the conference. Intel is looking to markets beyond the traditional PC to new, smarter mobile computing platforms. Mark summed it up like this: “Intel is no longer a one-size-fits-all company.”

Looking back, it’s interesting to recall a couple of events. First there was the great debate between TI on the SoC team and Intel on the system-in-package (SiP). At the time (I can’t recall how many years ago), Intel believed that it would be more cost-effective to bring various functionality together inside a package rather than monolithically on a single piece of silicon. Second was Intel’s XScale product line. XScale devices were once a hot topic amongst mobile device developers. But Intel sold the line to Marvell two-and-a-half years ago. What makes Intel circle back to SoC devices targeted beyond the traditional PC? Well, after the dust had settled on the Intel-TI SiP v. SoC debate and the XScale selloff, Apple introduced the iPhone. It’s success provided two key bits of information. First, it was possible for a smart phone to gain serious mass market appeal. Second, the iPhone suggested that a pocketable device was on the verge of being a serious computing platform. Now Intel returns to SoC, and it certainly has the manufacturing prowess to have a big impact in this space. Incidentally, part of Mark Bohr’s presentation touched on continued integration using the Atom core as a building block. Perhaps Intel intends to compete with ARM rather than license their technology as they did in the past with the XScale devices.

The bottom line is that Intel’s renewed interest in SoC technology is going to accelerate the development of ultra-portable computing platforms. Declining sales of the traditional desktop pc are fueling Intel’s move towards other markets. Growth in netbook sales and sockets for the Atom and similar devices are offsetting a lot of the loss in demand for more powerful microprocessors. But the netbook is only an transitional product. Computing is going more portable, and Intel will be ready.

Leaving things until the last minute is certainly nothing new for me, but I might be better off waiting to summarize next week’s IEDM than trying to preview it here. These days, there is a constant flow of negative news in the chip industry and the wider economy, so thinking about the research and development side of things for a while is a welcome break. Those actually at the conference may not have the luxury of avoiding the recessionary indicators since widespread cost-cutting is sure to make the event much smaller than usual. At least moving around at the coffee breaks will be easier.

Back to the concept of the preview, I had the really good fortune to speak directly to both IBM and Intel about their upcoming papers. Mark Bohr promoted presentations from three different technology angles that will appear at IEDM this year. The highlight is certainly the late news paper that Sanjay Natarajan will present. Sanjay is the Manager of Intel’s 32nm CMOS Technology Development and will provide a little more information on what is coming from their second generation HKMG. The emphasis will be on “little.” Intel rarely discloses much about their processes, but they have already released a couple of key metrics:

World’s tightest gate pitch of 112.5nm, and
World’s best drive currents – 1.55µA/µm for NFET’s and 1.21µA/µm for PFET’s.

You may see a pattern here. Intel likes to be way out front when it comes to numbers like this, and they certainly plan and make the investments necessary to achieve and maintain their lead. Last year at the Intel Developer Forum, Sanjay noted that the release of their first 32nm SRAM test chip was only 20 months after the 45nm version – well ahead of Intel’s already aggressive two year cadence for technology node introduction. Based on the combination of their process technology, transistor performance and timing production ramps for these nodes, Mark Bohr believes that Intel is “more than one generation ahead of the rest of the industry.” But even if they won’t reveal details of their 32nm process, Intel never needs to say much to draw a crowd. Whatever it is will be big news at this conference. Intel + 32nm is bound to have everyone buzzing.

The second paper Mark Bohr presented to analysts is about enhancing Intel 45nm for low power and SoC applications. Of course, HKMG can give you very powerful transistors, but it can also give acceptable levels of drive while keeping power consumption way down. Chia-Hong Jan’s 45nm SoC paper will claim that the low power process achieves less than 1nA/µm leakage. That’s bound to help battery life as well as Intel’s push to gain a bigger piece of the hand-held computing market. Atom-based based netbooks are surely not the end game in Intel’s aspirations of becoming more accepted into more mobile and portable platforms. The SoC process includes finger capacitors and high Q inductor elements. I wonder what they will build with this technology. It’s worth a trip to the Intel job board to see what kind of analog and RF people they might be looking for.

The third paper touted by Intel PR for the upcoming IEDM takes a longer view. Marko Radosavljevic’s paper on InSb transistors takes a much longer view of the technology roadmap than the previous two entries. Marko’s talk will build on previous work that disclosed n-channel devices with the IEDM paper in p-channel InSb quantum well transistors. Although they have not integrated the two yet, the goal of this work is to create a complete complimentary logic platform to replace silicon in the 2015 time frame. Intel really takes the very long term view of maintaining Moore’s Law. It’s not just the next few ticks of the tick-tock strategy that keeps them busy. Of course, Intel also does a lot of work with exotic silicon devices like FinFET’s as well, but the new channel materials may end up actually requiring fewer changes to the approach to design and manufacturing of IC’s simply by sticking to a planar technology.

Speaking of upcoming ticks though, IBM is very excited about both its 32nm bulk foundry process and its progress towards a viable 22nm technology. Dr. An Steegen will present a paper outlining key features of IBM’s 32nm bulk process. It will be offered in two versions. The first to ramp will be a low power version. IBM will introduce a high-k metal gate stack for the first time at 32nm. Migrating to HKMG from conventional poly gates with SiON dielectrics offers a very low leakage option. This flavor will not employ any strain engineering to enhance carrier mobility. However, the high performance version adds all the well-known stress elements to increase FET drive current. IBM doesn’t pre-release those numbers, so get to the conference or check back here. Better yet, take a look over at EETimes because Mark LaPedus will be keeping the broader community well informed of all the key developments at IEDM as they occur. Dr. Steegen and her team are rightfully proud of their accomplishment in 32nm. They like to point out that their gate first approach to HKMG allows the freedom of conventional gate layout without the need for restricted design rules required by the replacement gate flow used by Intel.

The IBM team at Albany Nanotech is pumped up about their recent progress toward 22nm. Dr. Bruce Doris believes that the rest of the industry should be too. The team will discuss their world record 22nm SRAM that boasts a cell size less than a tenth of a square micron. Proving that an SRAM cell works at the 22nm built on standard 300mm tools is great news for the whole industry and will ease concerns over extending this conventional memory to future nodes. The IBM 22nm SRAM certainly proves the viability of conventional planar CMOS for the next few years, so neither design nor manufacturing flows need to be turned onto their heads by FinFETs or some other exotic device.

In the technology race between Intel and competitors like IBM and AMD, it often seems to boil down to a choice about what to keep. For Intel at 45nm, they kept dry litho but gave up on conventional layout and moved to a restricted set of design rules with regular parallel patterns to give their existing dry litho tools a chance to keep doing the job. On the other hand, IBM and its technology partners like AMD opted to invest in immersion lithography earlier which allowed them to stick with conventional polysilicon layout rules. But there is not avoiding either of these approaches. Intel is using immersion lithography at 32nm. IBM has talked about restricted design rules and computational lithography to get to 22nm and beyond. That makes it hard to pick the best technology. Or it makes it harder for an analyst to be wrong. Either way, I don’t plan to stick my neck out. My colleagues Ramesh Kuchibhatla and Dr. Vu Ho will be at the conference. Talk to one of them. Both are seasoned technology veterans and not shy about giving you their opinion.

I am in London this week and just wrapped things up at the Intertech-Pira Image Sensor Conference. It was an interesting event with a diverse programme. There was everything from cameraphones to disposable endoscopes to swarms of robotic surveillance insects. Wait. The bugs were just my own nutty comment lifted from IEEE Spectrum. After a day where a single conference session dealt with both cameraphones and tiny cameras placed on the ends of laproscopic surgical instruments, Technology Review was very timely with their news of a cameraphone microscope.

But there was more to the conference than pictures of internal organs (right before lunch, thank you) and discussions of better ways of yanking gall bladders out through small pipes stuck into people.

What was hot? Well HDR – or high dynamic range – was. However, the definition of HDR was nowhere near consensus. HDR capability will be required in both security cameras as well as forward looking driver assistance cameras for cars. The other technology worth watching is backside illuminated imagers. Although it was not a featured topic in a session or even a single paper, it did pop up again in a few interesting places. I got turned onto the backside idea for the first time at IISW last May. Although it was introduced to me relatively recently, it’s been under investigation for a long time. Now it seems like it is picking up some momentum inside image sensor companies and starting to be considered for a potential production technology.

Sensors were not the only interesting discussion. Day two offered everything from the use of Flickr in image enhancement algorithms to shape memory alloys.

Graham Townsend, founder of Spiral Gateway, presented an interesting alternative to ASIC-based  Image Signal Processors (ISP). His team’s “soft” ISP approach avoids the 12 to 18 months lead time to get image processing algorithms hardwired into silicon. The obvious advantage is that the latest algorithms developed can be used in the cameraphone right as it goes into production, and they can be changed even after product launch simply by compiling new C code. Their chip is only slightly larger than a full custom ASIC providing the same processing (16 versus 14 square millimetres including I/O). The idea is based on RICA or re-configurable instruction cell array. Although I know virtually nothing about this architecture or other microprocessor alternatives, I would say the ISP application is only the tip of the iceberg. I can only explain it by borrowing one of Graham’s bullet points - ASIC netlists, wired up ‘on-demand’ in real time. (By the way, the iceberg analogy is quiteappropriate considering that co-chair, Lindsay Grant introduced Townsend by saying that Graham often referred to CMOS image sensors and imaging 10 years ago as just the tip of another iceberg.)

The shape memory alloys are being used by a company called 1…Limited to move the lens in an autofocus system. The alloy wire takes up almost no space (diameter is only 25 microns) inside the module providing space for larger lenses inside smaller modules. The next application of their wire is for adding zoom to future cameraphones.

Professor Raimondo Schettini from the University of Milano (Bicocca) gave an intriguing lecture on image enhancement techniques. These are more than the simple enhancements like automatic face detection or red-eye reduction that are so well known. His group has developed several algorithms for improving images based on decision trees to determine if the image is indoor or outdoor and so on to select the best algorithm based on determining the context in which the photograph was captured. A very interesting extension of that idea was the use of the web and the growing set of not only posted images but also user comments. This is visionary stuff. And I’m not just saying that because  my own presentation suggested that Google Street View might create the next image sensor boom! Professor Schettini intends to use the vast database available on Flickr to selectively apply algorithms to improve the image quality. As one slide pointed out, this is truly “data mining on all the available data.”
 
After IISW last May, this was my second chance to attend a relatively small meeting of image sensor technologists (and marketers as the case was this week). What I have discovered is that image sensor experts are not only extremely talented in their various fields but also a distinctly fun and classy group of people. I think there is a unique level of understanding within the imaging community that each sub-specialty represents only one part of a complex system that creates a final image and that all of the system components in delivering the final product are equally important.

Now an anecdote…I have a long and strange history of people getting my name wrong. I thought “Don” was pretty simple. I don’t know why, but the telephone company has listed me more than once as “Dan.” People I’ve met even several times often prefer “Dan” as well, but I thought everything would be okay here in London. I hoped I would come to a conference with my name correctly indicated in the programme (it was), give out some business cards with my name spelled properly (it was), and show a title slide with my name shown clearly as “Don,” and people would get it right. But I guess my parents were the ones who got it wrong. Within about 90 minutes of presenting yesterday, I was sitting at the same lunch table as an attendee who referred to me as “Dan the Insights guy.” I hope it doesn’t stick.

That’s all for Dan from London. (Well, if you can’t beat ‘em…)

Yesterday marked the dawn of a new era of scaling for CMOS devices. I hope that statement fits with all the hype around the launch of the 45nm microprocessor from Intel. In fairness, though, switching to metal gates and high-k dielectrics represents an important milestone in semiconductor technology. Gordon Moore’s well-worn comments are appropriate:

“The implementation of high-k and metal materials marks the biggest change in transistor technology since the introduction of polysilicon gate MOS transistors in the late 1960s.”

Intel released TEM images of its 45nm PMOS transistor. The embedded SiGe source / drains are evident, but we’ve all seen those before. For his keynote, Paul Otellini seemed confident that we could not tell what Intel’s secret sauce in the dielectric and workfunction metals was, but they had something to hide on top of the gate stack. We can’t see the CMP surface, but that’s a no-brainer for a replacement gate (aka gate last) technique. I think they want to keep the capping material on top of the gate electrode hidden until they present at IEDM (Paper 10.2). At about 9:30 on the morning of December 11 in Washington, DC, Kaizad Mistry will open the trench coat on the 45nm HKMG process. Considering the secrecy Intel has been able to maintain on this process, I think the trench coat is a fair reference. Intel deserves full marks for keeping its employees and vendors quiet for so long. Steve Jobs is jealous, I’m sure.

Or maybe he’s not. SI will be opening the kimono on the Penryn this Friday to all our clients participating in the analysis. Intel will still generate lots of excitement at IEDM (at least if you aren’t analyzing 45nm or buying one of our reports).

There’s been much hype and there will be much more.  The Penryn MPU hit Time magazine’s list of best inventions of 2007 along with the iPhone cover girl. Intel may covet the iPhone socket and may well win it for next generation devices, but there may could be another connection to Time’s list. NASA’s methane powered rocket might one day look to the Intel marketing machine as a steady source of fuel.

While attending the IBM and associates Common Technology Platform Forum this afternoon, it occured to me that I was bridging the gap between the design community and trying to get it right, and the failure analysis community that steps in too often to mention in polite company. That’s because I am also in San Jose to attend the International Symposium on Testing and Failure Analysis (ISTFA). The gap is more than a conceptual one as well since there are few if any slick executives at ISTFA. In fact, “engineer” is a word that is spoken in a somewhat unflattering fashion by many ISTFA presenters. But I refuse to hide my iron ring. (Big deal, I know since Canadians are in short supply at these events. Maybe at tonight’s Sharks game, it would be recognized but SI still hasn’t heeded requests to include pro-sports packages into corporate travel arrangements.) Since so many failure analysts are engineers, I guess it’s really designers – not engineers at large – that are the brunt of this abuse.

Intel Fellow Dr. Mario Paniccia enlightened the crowd with Silicon Photonics: Opportunity, Challenges & Applications. Dr. Paniccia is director of the photonics technology lab, but he got his start in quality and reliability at Intel. In fact, this appears to be how Intel decided that optical components on silicon made sense. It was the success of optical fault isolation and analysis tools used in silicon FA that got them thinking. If electro-optical interactions in silicon could be exploited for detecting failures, why not find a way to make photonic devices?

Without going into too much detail (I would not do it justice anyway), waveguides can be built very effectively on SOI. The game-changer for photonics is that silicon has patterning and processing tools available that are leagues ahead of the III-V equipment. As Dr. Paniccia said, the silicon photonics world can “draft” two or three generations behind Moore’s Law and still produce components that are beyond the wildest dreams of traditional photonics providers in terms of booth footprint and cost.

The trick to making this work is to get lasers and detectors onto silicon. Since silicon is an indirect bandgap material, emitters and detectors are better left to the compound semiconductors. But that is not a real set-back to the silicon developers because complicated packaging and assembly is still required of non-silicon components. Intel has developed ways to align multiple InP-based lasers onto their silicon waveguides at the wafer level. This work, done in collaboration with the University of Santa Barbara, has developed 30+ 40Gb/s parallel tranceivers. Get some more details from the Intel blog.

At this time, I would like to pass along my condolences to the III-V photonics community. With the Intel powerhouse on the verge of making your optical components as dirt cheap and tiny as today’s DRAM and flash, I believe your days are numbered.

The new buzz word – acronym actually – coming out of today’s IBM-Chartered-Samsung Common Platform Forum today here in Santa Clara is the term introduced by Qualcomm Senior VP and GM, Behrooz Abdi. His view of the consortium is to create an “integrated fabless manufacturer” or IFM akin to the IDM he means to displace. (Qualcomm has after all surpassed TI in the RF space perhaps leading TI towards its fab-lite ideas.)

IBM and its partners here are putting on a great show. Lunch is over now, and it’s time to get back to the sessions, but I will post more later. Unfortunately, that will be after things shut down back East.