Revealing commentary and news about the semiconductor industry.

Archives

‘Industry News’ Articles

Micron/Nanya debut 42nm SDRAM

42 nm 2Gb DDR3 SDRAM

Micron/Nanya's 42nm 2Gb DDR3 die, in volume production the second half of 2010

Seems like it was just last week (actually, 7 days ago to the hour) that Micron was unveiling its newest, smallest NAND flash process to date. This week, they’re at it again:  Jointly developed with Nanya, the 42nm 2Gb DDR3 SDRAM, with a 49.2mm2 footprint, packs 41.6 Mb into each square millimeter. Having just had a glimpse at the die from the top down, I dont’ have too much to go on, but let’s see what can be inferred from measurements alone. The 50nm 1Gb DDR2 part devoted 27.96mm2 to memory cells, while the 42nm part devotes 41.97 mm2 to memory cells, thus packing twice as many cells into 1.5 times the area. This .75 area shrink is a bit larger than the .71 area shrink one might expect from a linear shrink of 50 to 42nm. I haven’t lumped in peripheral circuitry, so one can’t blame the DDR3 IO circuitry overhead. These are pure memory cell numbers. It’s either additional redundancy(but nobody ever puts 5% redundancy), or the memory cell has not scaled commensurately with the node. There is precedent for this; even at 50nm, Micron’s 6F2 cell actually amounted to more like 7F2 owing to a relaxed bitline pitch. When we get actual SEM cross sections of this part (perhaps as you‘re reading this), I’m predicting the bitline pitch to be even more relaxed relative to the wordline pitch, which will likely be ~84nm to meet the 42nm standard. There’s an upper limit to this relaxation though. The bitline pitch can’t be allowed to approach 2.67F, or the area benefits of a 6F2 cell over an 8F2 cell will be negated.

Why can’t they just go with a 2F bitline pitch? It might have something to do with Micron’s use of wavy bitlines to minimize the oblique angle of their active regions, creating a more “straight“ (less leaky) access transistor. These bitlines have a longer average path length when snaking across the array and have a tighter effective pitch at the most sloped point in their wave cycle. This increase in line resistance and parasitic capacitance will hamper performance and may necessitate a relaxation in design rule to thicken the lines and space them out a bit more. If the performance doesn‘t get you, the litho might. Photoresist processes might experience failure points at the local pattern density increase. Additionally, it is more difficult to optimize off axis illumination for curvy patterns than it is for straight-line gratings. These concerns might force Micron at some point to stop riding the wavy bitline, but I’m sure the surf is still up in Boise. At 42nm, I’m expecting evolutionary change, not revolutionary.

Speaking of evolutionary change, let’s look into my crystal ball (single crystal silicon of course) and find out what else I think we’ll see in this part:

  • Storage dielectric – still a 3-layer sandwich of hi-K/hi-Barrier/hi-K using the same materials introduced at 50nm, with the hi-barrier making up a lower total fraction. It’s there for leakage prevention, but with a lower 1.35V supply voltage, the leakage barrier can be thinned to decrease EOT and still avoid FN tunnelling.
  • No spherical recessed channel access transistor. The SRCAT was a temporary boost in channel length for a few notable manufacturers in Korea, but it doesn’t scale well past 50nm, when the bulbous channels start to crowd each other.  Instead we’ll see ever deeper straight RCATs.
  • Capacitor aspect ratio over 10 to 1. Perhaps 12?
  • The dies we have were never packaged, so let’s make this interesting. I’m going to go out on a limb here and suggest copper bond wire. More conductive and cheaper than gold, copper is showing up as an option in many packaging houses. Copper wire plows through aluminum bond pads like a hot knife in butter, but Micron already has a nickel bond pad process in place. They’re all prepared for when gold hits $1300 an ounce.

Stay tuned – by the time you read this, UBM TechInsights process analysts will be able to paint a much clearer picture of the Micron 42nm SDRAM process and hopefully confirm some of my wild assertions above. Let’s hope it turns out better than my Superbowl bet…

Posted in Industry News, Memory, Process | 1 Comment »

 Page 1 of 53  1  2  3  4  5 » ...  Last »