SemiSerious

On March 20, the famous Gibson Guitar Corporation sued Harmonix, MTV, and EA for infringement of US Patent 5,990,405 – System and Method for generating and controlling a Simulated Musical Concert Experience. The defendants named are meant to cover the entire Guitar Hero series as well as the newer Rock Band game. Gibson has since expanded its suit to cover various retailers who sell the games including Wal-Mart.

Gibson Guitar Corporation’s complaint, filed in the Nashville Division of Tennessee District Court (courtesy of Wired’s Game|Life) specifies the alleged infringement like this:

THE INFRINGING PRODUCTS AT ISSUE
16. Defendants have and continue to manufacture and/or sell products that infringe, contribute to the infringement of and/or induce the infringement of at least claims 1, 13-15, 25 and 28 of the ‘405 Patent and/or have no other substantial noninfringing uses.

Considering how the music industry works today, you have to assume that Harmonix spent a lot of time and legal fee dollars working out licensing deals with record labels for the songs that appear in Guitar Hero. After all that work, it’s no surprise that they may have overlooked the possibility of a company outside the gaming world developing the concept first.

But that’s not all. According to SI device sourcing guru, Allan Yogasingam, ActiVision has already paid a license fee to Gibson for use of the signature Les Paul style of guitar for its game controller. The Les Paul image and brand is a lot more valuable (and stronger) than the patent cited in this case.

Before reading the complaint above, I read through the claims of the ‘405 patent trying to determine what angle Gibson’s lawyers were taking. There are four independent claims and 26 supporting claims. At least one independent claim needs to be map to the game system for Gibson to have a case.

Claim 13 is the broadest, but will it hold up to prior art scrutiny? How do karaoke machines fit in? Wikipedia suggests that the first machine was invented in Japan in the 1970’s. The entry for Karaoke history points out that the original inventor did not patent the machine. The Philippines granted a Letters Patent (UM-5269) in 1983 to its most famous inventor, Roberto del Rosario, for a system originally prototyped in 1975.

But one key element of ‘405 in all the claims is the use of a video interface as well. Although the earliest karaoke machines relied on singers to know the words or read them from a paper song sheet, video teleprompting entered the fray some time in the eighties. I may not be young and hip and part of today’s crowd of gamers, but I wasn’t quite hitting the karaoke bars back then. Perhaps one of my blogging elders could help me sort out more accurate dates for the introduction of video into the karaoke system. The ‘405 patent was filed in 1998 years after video technology was readily available to the karaoke set.

Claim 21 maps most directly to the game. It specifies a guitar. That is the focal point. Gibson’s lawyers arguments against the prior art hinge on the definition of “musical instrument.” It won’t be the first time a huge bill gets rung up over semantics, but this case will come down to whether singing into a microphone constitutes a musical instrument or not. Your favorite singer won’t get a vote.
 

Yesterday, the first departure from the post-Micron imaging company Aptina was announced. Dr. Ilia Ovsiannikov has moved to MagnaChip Semiconductor. As Image Sensor reported in detail, Ovsiannikov leaves the senior post at Micron of R&D manager and architect in Imaging to head up North American R&D for MagnaChip at their new design center in Pasadena.

Image Sensor speculated that perhaps Dr. Ovsiannikov preferred southern California to Aptina’s new home in San Jose. For those who spent time earlier in their careers nearer to the JPL birthplace of CMOS imagers in Pasadena, the urge to move south could prove too great.

For my own part, I have to wonder out loud if there will be more high-level departures out of Aptina.

I am in London this week and just wrapped things up at the Intertech-Pira Image Sensor Conference. It was an interesting event with a diverse programme. There was everything from cameraphones to disposable endoscopes to swarms of robotic surveillance insects. Wait. The bugs were just my own nutty comment lifted from IEEE Spectrum. After a day where a single conference session dealt with both cameraphones and tiny cameras placed on the ends of laproscopic surgical instruments, Technology Review was very timely with their news of a cameraphone microscope.

But there was more to the conference than pictures of internal organs (right before lunch, thank you) and discussions of better ways of yanking gall bladders out through small pipes stuck into people.

What was hot? Well HDR - or high dynamic range - was. However, the definition of HDR was nowhere near consensus. HDR capability will be required in both security cameras as well as forward looking driver assistance cameras for cars. The other technology worth watching is backside illuminated imagers. Although it was not a featured topic in a session or even a single paper, it did pop up again in a few interesting places. I got turned onto the backside idea for the first time at IISW last May. Although it was introduced to me relatively recently, it’s been under investigation for a long time. Now it seems like it is picking up some momentum inside image sensor companies and starting to be considered for a potential production technology.

Sensors were not the only interesting discussion. Day two offered everything from the use of Flickr in image enhancement algorithms to shape memory alloys.

Graham Townsend, founder of Spiral Gateway, presented an interesting alternative to ASIC-based  Image Signal Processors (ISP). His team’s “soft” ISP approach avoids the 12 to 18 months lead time to get image processing algorithms hardwired into silicon. The obvious advantage is that the latest algorithms developed can be used in the cameraphone right as it goes into production, and they can be changed even after product launch simply by compiling new C code. Their chip is only slightly larger than a full custom ASIC providing the same processing (16 versus 14 square millimetres including I/O). The idea is based on RICA or re-configurable instruction cell array. Although I know virtually nothing about this architecture or other microprocessor alternatives, I would say the ISP application is only the tip of the iceberg. I can only explain it by borrowing one of Graham’s bullet points - ASIC netlists, wired up ‘on-demand’ in real time. (By the way, the iceberg analogy is quiteappropriate considering that co-chair, Lindsay Grant introduced Townsend by saying that Graham often referred to CMOS image sensors and imaging 10 years ago as just the tip of another iceberg.)

The shape memory alloys are being used by a company called 1…Limited to move the lens in an autofocus system. The alloy wire takes up almost no space (diameter is only 25 microns) inside the module providing space for larger lenses inside smaller modules. The next application of their wire is for adding zoom to future cameraphones.

Professor Raimondo Schettini from the University of Milano (Bicocca) gave an intriguing lecture on image enhancement techniques. These are more than the simple enhancements like automatic face detection or red-eye reduction that are so well known. His group has developed several algorithms for improving images based on decision trees to determine if the image is indoor or outdoor and so on to select the best algorithm based on determining the context in which the photograph was captured. A very interesting extension of that idea was the use of the web and the growing set of not only posted images but also user comments. This is visionary stuff. And I’m not just saying that because  my own presentation suggested that Google Street View might create the next image sensor boom! Professor Schettini intends to use the vast database available on Flickr to selectively apply algorithms to improve the image quality. As one slide pointed out, this is truly “data mining on all the available data.”
 
After IISW last May, this was my second chance to attend a relatively small meeting of image sensor technologists (and marketers as the case was this week). What I have discovered is that image sensor experts are not only extremely talented in their various fields but also a distinctly fun and classy group of people. I think there is a unique level of understanding within the imaging community that each sub-specialty represents only one part of a complex system that creates a final image and that all of the system components in delivering the final product are equally important.

Now an anecdote…I have a long and strange history of people getting my name wrong. I thought “Don” was pretty simple. I don’t know why, but the telephone company has listed me more than once as “Dan.” People I’ve met even several times often prefer “Dan” as well, but I thought everything would be okay here in London. I hoped I would come to a conference with my name correctly indicated in the programme (it was), give out some business cards with my name spelled properly (it was), and show a title slide with my name shown clearly as “Don,” and people would get it right. But I guess my parents were the ones who got it wrong. Within about 90 minutes of presenting yesterday, I was sitting at the same lunch table as an attendee who referred to me as “Dan the Insights guy.” I hope it doesn’t stick.

That’s all for Dan from London. (Well, if you can’t beat ‘em…)

I would hardly be the first to speculate that creating a separate image sensor division with its own brand is part of a larger plan by Micron management to dump the unit now known as Aptina.

According to a quote from Bob Gove in EETimes, Aptina is targeting Japan and their 9 megapixel sensor is already “effectively penetrating the Japanese name-brand camera market.” But the rapid maturation of the cameraphone market has not been kind to CMOS image sensors, and I doubt that the digital still camera is the answer to rapidly declining margins and increasing pressure on sensor manufacturers to cut costs.

The Aptina announcement tried to focus on moving technology forward – something Micron’s CMOS image sensors excelled at. This year, Aptina will release a 1.4 micron pixel design manufactured using Micron’s 95nm copper process. But that was already on the roadmap and expected based on work Micron published at the International Image Sensors Workshop in 2007. The most interesting part of all the news is that Aptina is moving to supply complete camera modules. The silicon in a typical cameraphone module accounts for less than a third of the total manufacturing cost, so it made sense for the image sensor division to expand vertically into the supply chain. Module design offers not only the biggest target for cutting the camera production cost, but also shrinking the footprint taken up by the image capture system in cell phones. Aptina claims to be sampling the MT9V113M02STC VGA wafer-level camera in their product page. I suspect that part of the module design relies on something similar to Tessera’s OptiML WLC product announced last June.

After reporting a loss of $262 million in their last quarter, Micron is feeling more pressure to make changes and re-focus their business. Is this a sign of the investment community and Micron management being unwilling to take a longer-term view of the imager market, or are there simply no big growth opportunities left?

It must be painful for others in the image sensor business to listen to the news out of Boise over the last several months. Consider Micron’s history in this field. Their success in imaging has run parallel to the unprecedented rise of CMOS image sensor technology itself. Micron came out of nowhere to become the technology leader within five years. Of course the acquisition of Photobit and the pioneering work of Eric Fossum and others in 2001 pulled Micron up the learning curve. With the purchase of Avago at the end of 2006 along with their own in-house R&D in those five intervening years, Micron has an IP portfolio envied by nearly everyone else in the business.

Micron Imaging was an incredible story. Unfortunately, the emphasis might well be on the “was.”

From a management perspective, it seems baffling whether one should combine technology groups and divisions or to create several smaller entities. Is it better to consolidate and leverage economies of scale with “costs of sales” and the many other overhead costs associated with getting your technology into the market? Or will your corporate empire be better off with a loose affiliation of smaller, more entrepreneurial divisions less beholden to the politics and personalities of the big conglomerate?

Perhaps the decision between building a behemoth and keeping things simple and agile was not even on the minds of  Micron’s management. Maybe they were thinking less about how to run an imaging business than how to sell it by creating Aptina. 
 

This article originally appeared in EETimes Under the Hood. Unfortunately, there was an editing hiccup, so I have decided to post the complete text of the original article here. -Ed 

Two months after Semiconductor Insights provided the first public view of Intel’s 45nm technology and nearly a month after Intel’s IEDM presentation, it seems appropriate to revisit both the technology itself and what Intel was willing (and perhaps less willing) to reveal about it.

As noted on EETimes almost one month prior to the 2007 IEDM, the main features of Intel’s 45-nm technology are the incorporation of high-k hafnium-based dielectric material, titanium nitride (TiN) for the PFET replacement gate, and a TiN barrier alloyed with a work function tuning metal for the NFET replacement gate.

Although not the first 45nm node technology available on the open market, Intel’s process is the first to incorporate high-k metal gate (HKMG) technology. Panasonic (Matsushita) was actually the first to the 45nm node with an ASIC-optimized process using traditional polysilicon gates with SiON dielectrics.  This process is designed for density over performance and probably more indicative of the direction most manufacturers will be heading at 45nm. Density is certainly the key for the Panasonic process as it boasts several critical dimensions smaller than Intel’s.

Some high points of Intel 45nm HKMG technology are:

• High-k first, metal gate last integration
• Hafnium oxide (HfO2) gate dielectric (1.0nm EOT)
• Dual band edge workfunction metal gates
• TiN for PMOS
• TiAlN for NMOS

The gate last integration is one point that needs a bit of clarification in the Intel process flow.
Process Integration

Polysilicon gates may be gone in the final Intel 45nm products, but they are far from forgotten. A great deal of the transistor formation still depends on the polysilicon techniques that have dominated the industry for the last 40 years. In fact, the references to “first” and “last” refer to the order of the high-k and metal gate formation with respect to the polysilicon deposition.

It is now well-known that Intel uses a gate last or replacement gate process flow at 45nm. But there is an opportunity for a great debate of the semantics of the terms, whether it’s “gate” or “last.” I’m not predicting that the lawyers are already on their way, but there’s bound to be a patent out there that will create just such an argument.

The replacement gate flow allows Intel to reuse many process steps and tools from the age-old polysilicon gate technology. Patterning polysilicon and forming traditional silicon oxide and nitride sidewall spacers leverages tried and true self-aligned processes for source and drain formation and their lightly doped extension regions. Once these steps are completed, the polysilicon is removed and workfunction metals are deposited in their stead.

But there is something interesting going on even before the first poly deposition. Contrary to the suggestion in their IEDM paper, Intel deposits the first workfunction metal prior to the sacrifical gate polysilicon. For the P-channel transistor, titanium nitride (TiN) is deposited immediately after the HfO2 dielectric. Adding aluminum to form TiAlN tunes the workfunction for the N-channel transistors. There are a couple of ways to get the aluminum into the NFET’s gate, but I will not mention those here. In general terms, these primary workfunction metals are blanket deposited in their associated conductivity regions on the die.

Intel’s process protects HfO2 from the polysilicon etch by depositing the first workfunction layers before forming and patterning polysilicon. SI engineers refer to the first gate metal layer as the top interface layer (TIL) because of the undeniable protection it provides the HfO2 dielectric. The P-type metal gates are TiN while Al is added to create TiAlN and the appropriate workfunction for NMOS. Thicker layers of both metals are deposited in their respective N- and P-channel transistors after removing the sacrificial polysilicon and a barrier layer is formed on the bottom and sidewalls of the trench left behind by the polysilicon etch.

Making a final determination about whether the first or second layer of the workfunction metals is the most important in the Intel device would require additional mathematical treatment or computer simulations which are beyond the scope of this article. Is the primary gate the metal layer deposited before polysilicon or the one that comes after? To be fair, no one expects manufacturers to publicly disclose specific details of their processes. Either way, comments about the meaning of “gate” are arguably less important than the electrical performance of the finished product. Intel 45nm technology is certainly impressive in that regard. SI’s extraction of transistor electrical parameters indicates the following saturated drive currents at 1.0V and room temperature:

• PFET IDSAT = 1.08mA/µm
• NFET IDSAT = 1.36 mA/µm

Intel confirmed these values at their IEDM presentation in December (although our PFET number is actually 10µA higher than Intel reported). Not surprisingly, our results show higher drive currents at low temperature (-20°C) and reduced current at high temperature (85°C).

These high values for drive current evoke more questions regarding the gate structure. There has always been a discrepancy between the physical gate length, LG, of transistors and the shorter electrically active channel length, Lelec. But before the advent of modern metal gate technology, it was relatively easy to specify LG and compare transistor performance between fabs. The Intel gate structure creates some new problems for analysts.

Intel reports a gate length of 35nm which fits well with the 1.36mA/µm drive current generated by their NFET. However, the edge-to-edge dimension of their gate structure is closer to 45nm if measured in a fashion similar to the standard used for polysilicon gates. So what gives? The ratios of LG, Lelec and source/drain extension lengths would be out of whack to produce such large saturation currents.

The answer appears related to the question about the location of the metal gate’s edge. In the past, it was assumed that the entire width of the poly gate influenced carriers in the transistor channel. Since polysilicon is etched and replaced with a metal gate filling the trench in the gate last process, the situation is less straightforward. The first material deposited into the gate trench is not metal for the gate, but actually a barrier material, so the active portion of the gate is less than the traditional length measurement that would essentially run between the sidewall spacer on either side of the gate. The barrier is quite thin, though, so that would not account for the gate measurement difference.

What appears to set the electrically active gate length is the bird’s beak formed where the sidewall spacer meets the TIL. SI analysis concluded that this bird’s beak is the result of TIL and high-k etches undercutting the polysilicon. Re-oxidation of the polysilicon sidewall prior to silicon nitride spacer formation exacerbates the undercut. For the metal gate deposited into the trench, there is a thick, relatively low-k path toward the channel at this point that obviously could not electrically influence charge carriers in the region directly underneath the bird’s beak.

The critical portion of the metal gate could also be the TIL itself. Since this layer is composed of the same workfunction metal as the gate last layer, perhaps its edge defines the metal gate length. Fortunately, the edge of the TIL layer approximately aligns with the bird’s beak above it, so the choice of measurement point will not affect the value you get for LG.

The punch line to all of this is that the gap between gate trench edge and the electrically active edge of the workfunction metal (whether first or last) accounts for somewhere between 8 and 10nm. And that appears to explain the difference between Intel’s reported value for LG and what the rest of us have been looking at.
 
Despite its cure for leakage power, adding hafnium creates new headaches for the process integration engineer. Intel avoided hafnium’s downsides – threshold voltage pinning and reduced carrier mobility – by creating a silicon oxide (or possibly oxynitride) bottom interface layer (BIL) between the silicon substrate and the HfO2 layer. The BIL not only gets hafnium into the gate stack, it also gives the process engineer one more tuning knob. Since the gate dielectric’s influence on the transistor channel and electrical performance is a function of the individual contributions of the various layers, threshold voltages can be controlled by varying the BIL thickness for different transistor applications.
DFM

Process variability and designing for it are now hot topics as problems like line edge roughness and random dopant fluctuations become more problematic at 45nm.  This was addressed in Intel’s second presentation at IEDM 2007. Kelin Kuhn discussed improving yield by process improvements as well as design changes. The SRAM cell illustrated Kelin’s point as she showed the evolution from 90nm to 45nm design. The “tall” cell layout used at 90nm was replaced with a “wide” cell at 65nm.  The 65nm wide SRAM cell design improved dimension control and variability by aligning the polysilicon in a single direction and removing the corners in the active area patterns. At 45nm, Intel’s process removed “dog bone” and “icicle” shapes by employing only square end caps. These uniform structures are also easier to fill reliably in the gate last process.

Intel continues to use 193nm dry lithography at 45nm. Restricted design rules create “structured” gate layouts as Dr. Kuhn mentioned in her discussion of the SRAM cell. This DFM technique of uniform, regular arrangement of metal gates improves yields for the advanced HKMG technology without investing in new immersion tooling. Creating strictly rectangular gate patterns did require an extra step as double-patterning was used for the sacrificial polysilicon layer.

Many features of Intel’s 65nm process remain in evolved form. “Third-generation” strained silicon is used which is structurally similar to the embedded SiGe PMOS of their 65nm process. Nickel-salicide is also used again at 45nm. Intel employs dual damascene copper up to metal nine. SiCN barrier with carbon-doped oxide (CDO) create the low-k inter-level dielectric integration scheme.

Final Thoughts

However you slice it (pun intended), the Intel process is truly innovative. For technology analysts and pundits, it brings something fresh to the discussion –Moore’s (never-ending) Law, future trends, scaling and arguments about how they did it.

I want to thank Fayez Elchamaa, Vu Ho, Xu Chang and the rest of the crack Intel 45nm project team for their hard work. The SI analytical team has managed to piece together a large and complex set of data in order to provide both this brief overview along with the detailed analysis available to our clients.

Today Laura Peters from Semiconductor International (the other SI) hosted a webcast providing an overview of the contents of the upcoming 2007 Edition of the Semiconductor Industry Association’s (SIA) roadmap for technology - the ITRS. If there is anyone who really knows what’s in that upcoming document, it is Intel’s Alan Allan, and he gave the presentation. It’s the second time I’ve had the chance to listen to this Intel guru (see first time, here). This time Allan focused his thoughts on diversification of the ITRS to “more than Moore.” Scaling and Moore’s Law have been the rails for the semiconductor industry since its early days, but there is only so much that physical scaling can do and some places it’s just not at home.

The most obvious technology that gives us more without Moore is MEMS. Micro (or nano) electromechanical systems (MEMS) are at the heart of many systems from air bag deployment to Nintendo Wii game controllers. For Alan Allan and other industry luminaries, turning their attention to the critical part of consumer electronics systems to where the rubber meets the road is part recognition of the importance of the overall system or product and part realization that many aspects of scaling are creating more trouble than they are worth. Those troubles include increasing power consumption and capital consumption to get a cutting-edge chip designed, fabbed and into the market.

Sensors and actuators, or the way microelectronics actually interacts with our physical world, are a critical aspect of everything in our new digital age. Portable music players are ubiquitous primarily because of digital representation and storage of content, but they still need to drive something that can render an analog signal (that’s sound to a headphone if that last bit was too obtuse). You can add as much digital signal processing horsepower you want to a car, but it isn’t going to detect and correct a skid if there isn’t an analog detector at the front end of the signal path. And sensors - in particular MEMS devices - have no need for the latest lithography or the fastest transistors. MEMS technology is most at home in older, sometimes fully depreciated fabs.

Most of the “more than Moore” diatribe above is my own. I apologize and reward you for reading this far with a couple of comments made by the other ITRS representatives who were on hand for answering questions at the webcast. These actually relate more to Moore and traditional scaling issues.

When will EUV be ready? Will Conley, one of Freescale’s members of the lithography working group, answered that the next generation of litho will be ready for 22nm but not before. As for nanoimprint, he said this will only be used for “early device learning” until throughput can be improved.

I took note of a couple of other questions about interconnect. Chris Case (of the Linde Group) said there would not be a “materials” solution to inter-level dielectric constant below 2.0. He quickly added that there will be an air gap combination approach to get below k=2.0. Alan Allan also addressed the slowing of reductions in effective k values and many unresolved problems in technologies that are getting closer to their required introduction date (red brick wall for 2012). Chris Case also pointed out that 3D interconnect technology is well-proven in development fabs and will be ready when the industry is ready to take the plunge.

At the Common Platform Technology Forum last month, the design for manufacturing (DFM) session message was, “not if but when the industry will have to move to structured gate layouts.” Intel already has.

The industry is at a point where design for variability (DFV) is required. The old approach would be to add margin, but design margining has no scalability and no future.

A better option is to take a DFM approach that creates more litho-friendly designs. Intel has pushed out investment in new lithography tools, keeping their 193nm dry toolset at 45nm. Surely, one outcome of that decision was a requirement to use restricted design rules or a “structured” gate layout to improve yields. There is tangible evidence of this on the Penryn die. The metal gate lines are patterned in regular, parallel patterns to improve both printability and processing to maintain fidelity of the final structures. CMP is obviously a critical step in Intel’s gate last approach, and the structured layout also improves CMP. Filling the narrow trenches with the metal gate material must be easier too when there are fewer nooks and crannies in nice straight gate lines.

In an effort to maintain control of the message as information begins to leak out just before their IEDM presentation on Tuesday, Intel’s Kaizad Mistry provided a few nuggets to Semiconductor International. By restricting design rules to keep poly lines running in a single direction and switching to a wider SRAM architecture, Intel was able to push its SRAM feature size harder, Mistry said, adding that, “Many times, these design changes are beneficial for patterning.”Semiconductor International reports that Intel used double patterning lithography to “square off the ends of the patterns, reducing rounded ends (dogboning) and irregular shapes (icicles).” Looking at the Penryn deprocessed to tungsten metal 1, it is easy to compare the double-patterning used at the metal level to the tungsten trenches where it was not. According to Mistry, “There are benefits in terms of performance and layout density. The trench contact serves as a form of what you might say is local interconnect. And in terms of patterning, it is easier to pattern lines and spaces than a field of holes.”

I’m sure it’s not intentional, but the PMOS image released by Intel is a little misleading. At their paper on Tuesday at IEDM, look for Intel to clarify the situation by showing that the real story of their metal gate is much closer to the hafnium oxide high-k layer.

MIT Technology Review ran a very interesting story about printable electronics this week. Kovio, a company spun out of MIT’s Media Lab, announced a new process for printing transistors with inkjet printing techniques. According to this report, Kovio may begin production with disposable smart cards for public transit. Performance of Kovio devices will be better than what has been reported to date for IC’s created with commercial printing technology. The reason is that Kovio is the only group known to be applying this approach to inorganic materials.

Technology Review predicted several products for printed electronics including RFID tags and very large, full wall type displays. For a real potential boost to RFID adoption for inventory control, TR suggests that the cost of making an RFID tags this way could dip well below five cents.

But SI Senior Scientist, Dr. Ray Haythornthwaite, made these predicitions more than five years ago. In a report that was too early for its time or our sales force, Ray had already predicted electronic “wallpaper” that would change according to your mood or desire for instant redecorating. (Satisying my wife’s interior design whims would be so much easier if this product was available today.) The landmark, An Examination of Current Developments and Future Directions of Organic Semiconductor Technology (March 2002), provided a thorough examination of the early research into organic electronics and predicted the future for the technology. Everyone is still looking forward, but the field seems to be inching closer to making some real products.

Perhaps the killer app for ink-jet IC printing is the RFID tag. Ray also foresaw this as an obvious use for this technology. His rationale was that the packing box was there anyway, space was not (usually) at a premium. Why not just spray it on? Oddly enough, this outside-the-box thinking came at a time when our own spin-off company, Symagery Microsystems, was trying to break into the 2D barcode space. The transitioning of barcodes from 1D to 2D was evolutionary. The idea of printing a smart RFID tag to completely replace the barcode was certainly revolutionary. Ray is now retired from Semiconductor Insights but is available part-time for consulting in the semiconductor field. I don’t want to put his email here for spambots, but he is not hard to find on the web (not many Haythornthwaites in my phone book anyways).

Perhaps we can coin a new term in this nanotech era - millitech for millimeter-scale electronics. Using the ubiquitous ink-jet reverses some other trends - maybe even Moore’s Law. Millitech scaling trends and large scale integration would refer to ever-larger circuits covering more available real estate. This may put technology into the hands of ordinary people in contrast to the evermore exclusive club of megacorporations that can afford to build billion dollar wafer fabs. Consider one San Francisco artist who attempted to use nanobots as a form of high-tech graffiti, littering the little electronic insects around. Why not stick to a more traditional style of the art using spray cans? Different colors are replaced by the various transistor building materials, and voila! A new urban art form is born that can sense its audience, react and vary the imagery according to it.

Spray-on ICs - why not? Here are some links to some other, perhaps less-anticipated products offered in such a form:

http://gizmodo.com/gadgets/technology/spray-on-a-computer-133076.php

http://nexus404.com/Blog/2006/12/01/spray-condom/

http://www.cpr-savers.com/Industrials/bandas2/bandage%20spray.html

http://www.thisnext.com/item/21BD8AB8/NYC-Organic-Spray-On-Tan

http://www.uniquepaving.com.au/spray-on-paving.htm

Last week, I mentioned that Matsushita might not be getting the respect they deserved with a 45nm process obliterated by Intel’s shadow. I also should acknowledge that I was one of the doubters and expected Intel to not only get to 45nm first but with a considerable lead on second place. Well it turns out that the speculation by Engadget and others coming out of CEATEC was correct. Matsushita (or Panasonic) not only has a real 45nm logic process, but they beat Intel to the market!

Matsushita doesn’t bother with high-k gate dielectrics or metal gate electrodes at 45nm, but they achieve the transistor packing density of the latest technology node. In fact, the Matsushita process beats Intel’s tightest metal pitches. The DVD decoder chip is a complex SoC with over 300 small SRAM arrays scattered around the die. A compact die size of 68 square millimeters certainly would not be possible without a small bit cell design, and Matsushita’s SRAM cell size matches up with Intel. With slightly tighter than 140nm pitch at metals one through four, Matsushita actually has a slight edge over Intel’s 150nm observed pitch.

The UniPhier SoC is truly built to reduce silicon die area and cost. Believe it or not, Panasonic uses it in a video player with a VHS tape bay. That’s something old along with the new in the DMR-XW200V Blu-Ray player. There could be something borrowed as well, but we are still analyzing the device, and I’m not a lawyer.

Finally, let me extend a sincere apology to Matsushita for underestimating their prowess in process technology as well as a hearty congratulations for being the first manufacturer of 45nm logic technology.

Yesterday marked the dawn of a new era of scaling for CMOS devices. I hope that statement fits with all the hype around the launch of the 45nm microprocessor from Intel. In fairness, though, switching to metal gates and high-k dielectrics represents an important milestone in semiconductor technology. Gordon Moore’s well-worn comments are appropriate:

“The implementation of high-k and metal materials marks the biggest change in transistor technology since the introduction of polysilicon gate MOS transistors in the late 1960s.”

Intel released TEM images of its 45nm PMOS transistor. The embedded SiGe source / drains are evident, but we’ve all seen those before. For his keynote, Paul Otellini seemed confident that we could not tell what Intel’s secret sauce in the dielectric and workfunction metals was, but they had something to hide on top of the gate stack. We can’t see the CMP surface, but that’s a no-brainer for a replacement gate (aka gate last) technique. I think they want to keep the capping material on top of the gate electrode hidden until they present at IEDM (Paper 10.2). At about 9:30 on the morning of December 11 in Washington, DC, Kaizad Mistry will open the trench coat on the 45nm HKMG process. Considering the secrecy Intel has been able to maintain on this process, I think the trench coat is a fair reference. Intel deserves full marks for keeping its employees and vendors quiet for so long. Steve Jobs is jealous, I’m sure.

Or maybe he’s not. SI will be opening the kimono on the Penryn this Friday to all our clients participating in the analysis. Intel will still generate lots of excitement at IEDM (at least if you aren’t analyzing 45nm or buying one of our reports).

There’s been much hype and there will be much more.  The Penryn MPU hit Time magazine’s list of best inventions of 2007 along with the iPhone cover girl. Intel may covet the iPhone socket and may well win it for next generation devices, but there may could be another connection to Time’s list. NASA’s methane powered rocket might one day look to the Intel marketing machine as a steady source of fuel.