SemiSerious

Today Laura Peters from Semiconductor International (the other SI) hosted a webcast providing an overview of the contents of the upcoming 2007 Edition of the Semiconductor Industry Association’s (SIA) roadmap for technology - the ITRS. If there is anyone who really knows what’s in that upcoming document, it is Intel’s Alan Allan, and he gave the presentation. It’s the second time I’ve had the chance to listen to this Intel guru (see first time, here). This time Allan focused his thoughts on diversification of the ITRS to “more than Moore.” Scaling and Moore’s Law have been the rails for the semiconductor industry since its early days, but there is only so much that physical scaling can do and some places it’s just not at home.

The most obvious technology that gives us more without Moore is MEMS. Micro (or nano) electromechanical systems (MEMS) are at the heart of many systems from air bag deployment to Nintendo Wii game controllers. For Alan Allan and other industry luminaries, turning their attention to the critical part of consumer electronics systems to where the rubber meets the road is part recognition of the importance of the overall system or product and part realization that many aspects of scaling are creating more trouble than they are worth. Those troubles include increasing power consumption and capital consumption to get a cutting-edge chip designed, fabbed and into the market.

Sensors and actuators, or the way microelectronics actually interacts with our physical world, are a critical aspect of everything in our new digital age. Portable music players are ubiquitous primarily because of digital representation and storage of content, but they still need to drive something that can render an analog signal (that’s sound to a headphone if that last bit was too obtuse). You can add as much digital signal processing horsepower you want to a car, but it isn’t going to detect and correct a skid if there isn’t an analog detector at the front end of the signal path. And sensors - in particular MEMS devices - have no need for the latest lithography or the fastest transistors. MEMS technology is most at home in older, sometimes fully depreciated fabs.

Most of the “more than Moore” diatribe above is my own. I apologize and reward you for reading this far with a couple of comments made by the other ITRS representatives who were on hand for answering questions at the webcast. These actually relate more to Moore and traditional scaling issues.

When will EUV be ready? Will Conley, one of Freescale’s members of the lithography working group, answered that the next generation of litho will be ready for 22nm but not before. As for nanoimprint, he said this will only be used for “early device learning” until throughput can be improved.

I took note of a couple of other questions about interconnect. Chris Case (of the Linde Group) said there would not be a “materials” solution to inter-level dielectric constant below 2.0. He quickly added that there will be an air gap combination approach to get below k=2.0. Alan Allan also addressed the slowing of reductions in effective k values and many unresolved problems in technologies that are getting closer to their required introduction date (red brick wall for 2012). Chris Case also pointed out that 3D interconnect technology is well-proven in development fabs and will be ready when the industry is ready to take the plunge.

Last week, I mentioned that Matsushita might not be getting the respect they deserved with a 45nm process obliterated by Intel’s shadow. I also should acknowledge that I was one of the doubters and expected Intel to not only get to 45nm first but with a considerable lead on second place. Well it turns out that the speculation by Engadget and others coming out of CEATEC was correct. Matsushita (or Panasonic) not only has a real 45nm logic process, but they beat Intel to the market!

Matsushita doesn’t bother with high-k gate dielectrics or metal gate electrodes at 45nm, but they achieve the transistor packing density of the latest technology node. In fact, the Matsushita process beats Intel’s tightest metal pitches. The DVD decoder chip is a complex SoC with over 300 small SRAM arrays scattered around the die. A compact die size of 68 square millimeters certainly would not be possible without a small bit cell design, and Matsushita’s SRAM cell size matches up with Intel. With slightly tighter than 140nm pitch at metals one through four, Matsushita actually has a slight edge over Intel’s 150nm observed pitch.

The UniPhier SoC is truly built to reduce silicon die area and cost. Believe it or not, Panasonic uses it in a video player with a VHS tape bay. That’s something old along with the new in the DMR-XW200V Blu-Ray player. There could be something borrowed as well, but we are still analyzing the device, and I’m not a lawyer.

Finally, let me extend a sincere apology to Matsushita for underestimating their prowess in process technology as well as a hearty congratulations for being the first manufacturer of 45nm logic technology.

While attending the IBM and associates Common Technology Platform Forum this afternoon, it occured to me that I was bridging the gap between the design community and trying to get it right, and the failure analysis community that steps in too often to mention in polite company. That’s because I am also in San Jose to attend the International Symposium on Testing and Failure Analysis (ISTFA). The gap is more than a conceptual one as well since there are few if any slick executives at ISTFA. In fact, “engineer” is a word that is spoken in a somewhat unflattering fashion by many ISTFA presenters. But I refuse to hide my iron ring. (Big deal, I know since Canadians are in short supply at these events. Maybe at tonight’s Sharks game, it would be recognized but SI still hasn’t heeded requests to include pro-sports packages into corporate travel arrangements.) Since so many failure analysts are engineers, I guess it’s really designers - not engineers at large - that are the brunt of this abuse.

Intel Fellow Dr. Mario Paniccia enlightened the crowd with Silicon Photonics: Opportunity, Challenges & Applications. Dr. Paniccia is director of the photonics technology lab, but he got his start in quality and reliability at Intel. In fact, this appears to be how Intel decided that optical components on silicon made sense. It was the success of optical fault isolation and analysis tools used in silicon FA that got them thinking. If electro-optical interactions in silicon could be exploited for detecting failures, why not find a way to make photonic devices?

Without going into too much detail (I would not do it justice anyway), waveguides can be built very effectively on SOI. The game-changer for photonics is that silicon has patterning and processing tools available that are leagues ahead of the III-V equipment. As Dr. Paniccia said, the silicon photonics world can “draft” two or three generations behind Moore’s Law and still produce components that are beyond the wildest dreams of traditional photonics providers in terms of booth footprint and cost.

The trick to making this work is to get lasers and detectors onto silicon. Since silicon is an indirect bandgap material, emitters and detectors are better left to the compound semiconductors. But that is not a real set-back to the silicon developers because complicated packaging and assembly is still required of non-silicon components. Intel has developed ways to align multiple InP-based lasers onto their silicon waveguides at the wafer level. This work, done in collaboration with the University of Santa Barbara, has developed 30+ 40Gb/s parallel tranceivers. Get some more details from the Intel blog.

At this time, I would like to pass along my condolences to the III-V photonics community. With the Intel powerhouse on the verge of making your optical components as dirt cheap and tiny as today’s DRAM and flash, I believe your days are numbered.

The new buzz word - acronym actually - coming out of today’s IBM-Chartered-Samsung Common Platform Forum today here in Santa Clara is the term introduced by Qualcomm Senior VP and GM, Behrooz Abdi. His view of the consortium is to create an “integrated fabless manufacturer” or IFM akin to the IDM he means to displace. (Qualcomm has after all surpassed TI in the RF space perhaps leading TI towards its fab-lite ideas.)

IBM and its partners here are putting on a great show. Lunch is over now, and it’s time to get back to the sessions, but I will post more later. Unfortunately, that will be after things shut down back East.

Words cannot adequately describe my excitement when I first dug into the latest edition of the ITRS and discovered that the idea of process or technology node had been eliminated. It seemed like a dream, but it was driven home when I listened to Alan Allan?s presentation at a Sematech-Semico joint event last January.

The new industry standard for specifying a number to describe an IC technology is to use a real measurement. Manufacturer marketing and industry analysts alike should now devote themselves to eliminating the dangerous and confusing “spin” that has led to so much confusion over the years. When is a “90nm process” not 90nm? What’s the difference between a 70nm and a 73nm NAND process?

For casual industry observers and corporate marketing spin-doctors, there seems to be a tendency to jump on the number with the best ring to it. This mis-information drove the SIA to take a clear stand promoting the use of unambiguous numbers and technology definitions. It makes sense. You measure a real dimension - like the wordline pitch - and translate it to the attainable mask dimension for a repetitive structure which is actually one-half of the pitch. Here is the most important part:

specify the thing you measured.

Unfortunately, the confusion continues. Doubt is cast upon numbers coming from manufacturers and analysts alike. Consider the recent example of the so-called Samsung 60nm NAND*. The product development team published the technology at the 2005 ISSCC ? ?An 8Gb Mult-Level NAND Flash Memory with 63nm STI CMOS Process Technology.?? An actual physical 60nm part makes little sense if you already have 65nm in production. Although Samsung?s press release is not using 60nm in the strict sense of a physical measurement, it does point out that the previous generation of NAND memory was 70nm ? not 65nm.

The most advanced generation of Samsung flash available is 64?1nm as measured from the wordline half-pitch. Semiconductor Insights has analyzed this memory extensively and published several reports on the findings. Semiconductor Insights believes the next stop on the Samsung flash roadmap is 55nm. Will we measure 55 exactly? I would bet against it, but we won?t be calling it 50nm.

It gets tricky when one either disputes or attempts to differentiate independent measurements or specifications that differ by only a few nanometers. Of course, this assumes a certain level of care and expertise on the part of those who publish their measurements. Alas, some analysts have made horrible blunders and produced erroneous measurements while blinded with a preconceived notion about what they would find. I will do my best to keep the numbers published here honest, accurate, and most importantly, unambiguous.

*The newest technology advancement brings 25 percent higher manufacturing productivity over the previous 70nm design technology. The newest technology advancement brings 25 percent higher manufacturing productivity over the previous 70nm design technology.?(Samsung press release, July 19, 2006)