SemiSerious

Toshiba's LaAlO3/SrGeX/Ge p-MISFET Gate Stack

I mentioned elsewhere that Intel’s approach of removing the oxide interlayer prior to high-K dielectric deposition was a significant advance on the road to scaling HKMG processes for the 16nm node.  This  joint effort with Sematech and UT Dallas will be presented at VLSI Technology Symposium 2009. Intel’s oxide-less gate stack technique might be signaling the direction they will be taking for future high-K processing which has a big impact on the rest of the logic manufacturers.

Although I overlooked the non-silicon channel transistor presentations at VLSI 2009, they are certainly a serious contender for future generations like 16nm. Intel themselves spend a great deal of effort seeking a silicon channel replacement. Many of my trusted colleagues believe that a new material will displace silicon for the transistor channel thereby extending the scalability of planar complimentary logic and avoiding the use of multiple gated, vertical channel transistors such as the FinFET. Of course, it’s a dangerous game to point to one Intel paper about technology that’s three nodes down Sheriff Moore’s road when Intel always explores as many technology options as possible before deciding on a direction for future production.

Intel has been busy pursuing possible replacements for silicon as the channel material for transistors., but they certainly aren’t the only ones as Toshiba’s presentation Monday afternoon in Kyoto proves.

In Session 4B devoted to the germanium MOSFET, Toshiba will present “New Approach to Form EOT-Scalable Gate Stack with Strontium Germanide Interlayer for High-k/Ge MISFETs.” The Toshiba paper claims the highest ever hole mobility in a p-channel FET with a peak value quoted of 481cm2/Vs. With only the abstract and the TEM image provided in the Toshiba release, it’s difficult to say how close they are to providing a viable solution for the equivalent oxide thickness (EOT) target of 0.5nm for the 16nm logic generation. The press release reports the cost of the strontium germanide interlayer is to increase the EOT by “only 0.2nm at the most.” It appears that the gate stack reported by Toshiba achieves a total EOT of “as thin as around 1nm.”

Toshiba has clearly done some great work in this area. They have also clearly demonstrated the LaAlO3/SrGeX/Ge p-MISFET as a technology option. But there are many hurdles standing between this work and getting this gate stack ready for the 16nm node. There appears to be less standing in the way of the Intel zero SiOx interface stack which claims an EOT of 0.59nm. That Intel-Sematech-UT Dallas paper will be presented in the Advanced Gate Stacks Session (3A) just a couple of hours before Toshiba.

One thing I really like about this paper is its return to the term MISFET which was sadly replaced long ago by the now familiar MOSFET.  For the PR professional, it’s all too close to misfit, of course, but in this new age of non-oxide gate dielectrics and even non-silicon channel materials, a more generic term is needed. Oddly, even the session title for Toshiba’s paper is “Ge MOSFET,” but as their abstract says, the strontium-germanide interlayer avoids the low-K oxides of germanium for the gate dielectric in their germanium channel devices. Still, I hope that even if an oxide ends up in the mix for whatever direction the industry widely adopts, we can keep MISFET because geeks – especially semicon geeks – like to think of themselves at least a little bit like misfits.

This week marks the beginning of the long and sometimes arduous process of selecting winners in the SI Insight Awards in each of the technology categories. Of course, these are:

• Process Technology
• Non-volatile Memory
• DRAM
• Mobile Processor

Of course, it’s always a treat to talk to the creators of technology about their products. Sometimes, it’s more like listening to proud parents talk about their kids, but that isn’t always as painful as it sounds – unless you don’t like kids. Well, at SI we love the little offspring of all the different product groups out there. Dealing with the media relations, marketing groups and product managers means hearing lots about what sets each product apart from the competition. Ultimately, though, a seasoned group of Semiconductor Insights analysts will judge each entry on its significance to the industry as a whole.

The arduous part of this is sometimes comparing technologies that may not compete directly against each other in a product or technology space. Does the smallest feature size guarantee a Process Technology winner? Then, obviously, a memory device, or more likely, a flash memory device would always win. Maybe you have to discount the perfectly repetitive structure of the memory array and look at how dense the manufacturer packed in the logic gates. Alas, this would exclude a memory chip from winning since their digital circuits typically employ design rules miles behind both its own memory cells as well as leading edge pure logic devices like microprocessors.

Time to stop talking and start thinking about narrowing down the list of finalists in each of the categories. I certainly hope that this year’s Insight Awards inspire the creation of more leading edge devices (or at least their submission to our awards program) in 2009.

Toshiba is the first flash manufacturer to incorporate a high-K dielectric in their product. Their innovative inter-poly dielectric has allowed Toshiba to scale their floating gate flash memory to 43nm. The 16Gbit multi-level cell (MLC) device from Toshiba sets the new high watermark for NAND flash bit density at 139Mbits/mm².

Samsung claimed the first implementation of high-K dielectric for flash. However, that was for a charge-trapping (CTF) device they expected to roll out for 4Xnm. By now, we have all heard a lot about TANOS flash from Samsung. There is no floating gate with CTF, so the high-K material is in the tunnel oxide between the silicon channel and the control gate of the memory cell. The TANOS concept first announced by Samsung at IEDM 2005 was an extension to the generic SONOS approach of an oxide/nitride/oxide sandwich for charge trapping much like the so-called O-N-O inter-poly dielectric routinely used to separate the control and floating gate in traditional flash devices. The SONOS acronym was derived from the silicon on top (poly gate) of the dielectric and the silicon substrate underneath. SANOS CTF devices increased the dielectric constant of the charge trapping dielectric to allow the layers to electrically scale without sacrificing reliability by physically thinning the layers. The ‘A’ in SANOS comes from the aluminum-oxide high-K material. The last step to get to TANOS was for Samsung to substitute a tantalum-nitride metal gate in their CTF.

The bottom line from that wordy, acronym-laden paragraph is that floating gate was supposedly running out of steam and CTF devices were going to replace them. That’s what generated all the buzz and all the lovely new acronyms. Despite many “expert” predictions over the years, reports of the death of floating gate flash are greatly exaggerated. On the contrary, floating gate technology continues to dominate the market. I wonder if the floating gate technologists at Toshiba are having a good laugh because they were first to market with high-K which was a big part of the CTF that was supposed to put them out of business.

Many more details on this innovative flash process from Toshiba are available from Semiconductor Insights.

For years the question, “How much is enough?” has been debated regarding NAND flash endurance. How many write cycles do you really need over the lifetime of a camera card or memory stick? How long do you need your portable data to stay intact?

SI’s senior memory analyst, Young Choi, attended the recent Flash Memory Summit in Santa Clara to hear what the vendors are saying about solid-state drives, or SSD’s. As NAND flash prepares to reach out and grab a chunk of the hard disk drive market, it will face even more scrutiny as we will all demand more endurance from the SSD’s that are just beginning to show up in select computers. As Young noted, “The overall impression is that the market is still in its infancy and it will take quite a while before enterprises and consumers adopt systems with SSDs.” And that was certainly the view of Fujitsu who cautiously observed, “the market and consumer are not happy about SSD overall.”

Participants were focused on three areas – performance, endurance and price. Many experts are calling for standardization of SSD performance metrics to eliminate the current state of confusion over SSD performance metrics. That would help avoid the “benchmarketing” we are often forced to suffer in this industry.

When I mentioned the NAND flash endurance debates of the past, I was alluding to the MLC versus SLC wars that have been waged over the years (often with Toshiba and Samsung as the respective combatants). The key information returned from the Summit was based on a usage model of 20GB per day for the typical consumer. This means that MLC NAND flash could provide sufficient lifetimes for consumer SSD products.

Several summit participants tried to predict the future of the SSD market by comparing it to the HDD market of long ago. Expect some major rounds of consolidation considering that there are more than 70 SSD manufacturers today.

But it seems like there is more driving SSD technology than simple bits and drive endurance. There is a shade of green overtaking the SSD conversation. Yes, saving energy and “going green” is a big part of the talk about SSD’s. At the Summit, the local California utility, PG&E, promoted the need to reduce energy demands through technological innovation. Their example was the power consumed by large data centers which can be reduced by transitioning to SSD.

Young mentioned that Intel will have some interesting things to discuss at the Intel Developer Forum August 19 through 21. Intel may concentrate on the controller for SSD, and this may actually be the key component to making NAND work in the SSD. The way operating systems use the hard disk is really tough on flash. For robust SSD’s in our future laptops, we will be relying on Intel and others to implement intelligent control and management of which physical memory locations are used to even out the wear over the whole flash chip over the life of the product. SanDisk has proposed their own version that they are calling LDE or Long Term Data Endurance.

For years, there has been speculation that traditional SRAM would be replaced with a denser type of memory for SoC devices. In fact, TI once announced that they would use ferroelectric RAM or FeRAM beginning at 90nm for their devices. Fear of ever-worsening process variability has been widespread. Alas, we have entered the 45nm period, and SRAM continues to be the workhorse of the industry.

I’m not suggesting there has been no competition. Once upon a time, it was popular to use a DRAM cell, hide the refresh inside a circuit macro, and call it 1T-SRAM.

But why have these alternatives either never been used (FeRAM and others), lost favor (as it seems in the case of 1T-SRAM and eFlash), or been relegated to only very high density, very high speed applications (as with DRAM)? But don’t expect an answer, I’m just posing these questions – at least for this week. Winter has weighed me down too much to think about such things.

DRAM has enjoyed some success, so let’s take a closer look. The bits are denser. A DRAM cell occupies only eight times the minimum area unit of a given process technology versus about 120 or more for an SRAM cell. Looking at it this way, SoC DRAM should be a no-brainer right? Wrong. The DRAM is dynamic RAM. That is, leakage in the cell access transistor will erase the contents of the cell. So the cell has to be refreshed. The circuit overhead for cell refresh along with some other operations means that the DRAM taken as a complete circuit macro will only be smaller than an SRAM for densities beyond about 4MB.

Until very recently, SoC DRAM has been narrowly confined to graphics processors from gaming consoles. Microsoft, Nintendo, and Sony game systems have all used graphics engines that integrated large embedded DRAM (eDRAM) arrays onto their chips. The semico’s that actually produced the chips were ATi/NEC, IBM, and Sony/Toshiba. IBM has enjoyed a long history in the development of DRAM and embedded DRAM. IBM invented trench capacitor DRAM, and this type has become the de-facto standard for SoC devices. I say that despite NEC’s stacked capacitor structure used in one of the XBOX 360 chips. In fact, the ATi/NEC chip is a very special case of eDRAM. It’s really more of a DRAM with integrated memory controller. Dick James has some interesting thoughts on eDRAM in game consoles that you can reach with this link.

The Sony gaming consoles are an interesting case study. Consider this. PS2 and PS3 consoles contained graphics engines with eDRAM. However, the hand-held PSP does not. Instead, a commodity DRAM die is packaged, SiP style, along with a pure logic LSI device. You might say that portable devices need to be more energy efficient and would demand the use of single-chip solutions over multiple die which typically suck more power. But there is more price and manufacturing cost pressure on the PSP driving Sony’s choice for the portable platform. High development and process integration costs are certainly limiting the use of eDRAM. I think the lesson from Sony is actually more general and addresses the whole SoC versus SiP debate.

My take is that eDRAM will only ever exist in a couple of places. It will continue to provide extremely large on-chip arrays for memory-hungry special purpose graphics processors. It will also become more common where bits need to be neatly packed along the columns of an LCD driver. But once again, this will only be for extremely memory intensive applications such as mobile drivers with very large color depth.

Other than that, SRAM will reign supreme. For the best example, look at the Qualcomm MSM7500 die micrograph at the top of this post. For a complicated SoC architecture like this, embedding DRAM makes no sense. Another example of SRAM maintaining its foothold is the latest 45nm MPU. Since Intel still did not integrate a memory controller onto the Penryn, the design still relies on a huge 6MB L2 cache, but it’s still good, old-fashioned SRAM.

With the VLSI Syymposia just a little over a month away, I will wrap up my picks for papers to watch for by looking at DRAM. For the Technology Symposium, Samsung is over-represented with five out of the seven presentations split between two sessions.

Two of Samsung’s articles will discuss aspects of their FinFET DRAM cell, touted as the enabler for sub-50nm devices. The second paper appears to provide more details of the process and cell performance. If enough details are provided at the conference, it could be enough to predict Samsung as the first to make it to production with a FinFET device.

Qimonda is the only other vendor presenting a technology paper. In their forward-looking work, carbon is proposed as a new capacitor electrode material for DRAM. The technology includes a high-K dielectric for the trench capacitor, so Qimonda moves to carbon-based materials for better thermal stability. Qimonda’s other paper promotes trench technology beyond 40nm with a discussion of an array transistor that is self-aligned to the trench.

But the best paper for insight into production technology is provided in the final DRAM paper. Samsung announces it’s 56nm, 1Gb technology patterned on an ArF immersion tool. A 0.19 square micron cell size is reported. To achieve this scaled cell, Samsung moves to an elevated source / drain structure for the first time. Micron has used a similar structure for a few generations now. The capacitor dielectric is “ZAZ” which is a sandwich of zirconium and aluminum oxides for increased K value. Based on some work shown by Kinam Kim at IEDM 2005, I expect that the higher aspect ration capacitors at 56nm could use the Samsung “MESH-CAP” design for mechanical stability.

In yet another article, Samsung talks about hafnium dielectrics for DRAM. Of course, we have already seen this used in capacitors, but this work describes hafnium in a HfSiON dielectric for the access transistor.

Samsung is the DRAM dominator, and they lead this conference along with many others in presenting their technology developments. Unfortunately, I will not have a chance to see any of these papers first hand, but my good friend and colleague, Ramesh Kuchibatla will be in Kyoto and provide both scoops and scams he discovers at the event.

This is my second review of papers to be presented at the VLSI Technology Symposium. Today, I will take a look at the most promising papers on phase change memory technology (PCM or PRAM). Today at its spring development forum in Beijing, Intel announced that it will produce a 128M 90nm PRAM later this year. This is bound to create some extra buzz around the many good PRAM papers to look forward to at VLSI.

Samsung dominates the PRAM submissions as you might expect from some of their announcements in the past year. They will present a phase change cell based on GeSbTe for sub-50nm generations that appears to keep reset current below 260µA.  PRAM designs typically suffer from high currents required to heat and change the phase of the active layers. In another paper, Samsung memory engineers plan to present a novel heat dissipating cell scheme to improve the reset characteristics across a large (512M) array.

Naturally, Intel does have a paper in the NVM category. Oddly, though, it is a traditional floating gate NOR. Intel’s flash team will present “A Scalable Self-Aligned Contact NOR Flash Technology.” Sounds a bit bland, but it promises technology for 40nm and beyond. At 65nm, the cell area is only 0.036 square microns which is a cell area factor improvement from 10.6 on their 65nm production technology down to 8.5. This team’s ability to push the floating gate NOR cell is somewhat at odds to the PRAM announcement that was billed – in the EETimes article anyway - as the replacement for the floating gate.

In a way, it makes sense for Intel to get PRAM into the market first. But you need to look back a few years before STMicroelectronics began to make big strides and invest a lot of energy in PRAM development. Intel was the first major player to invest in phase change memory by funding a spin-off from the creators of ovonics. Energy Conversion Devices was the corporate entity that grew out of the pioneering work of Stanford R. Ovshinsky in 1960. A separate company – Ovonyx – was formed in 1999 to commercialize the “Ovonic Unified Memory” or OUM. Today, OUM has a sexier name. PRAM is “perfect RAM” in the Samsung vernacular.

That’s enough of a history lesson though. It does sound as though we will have a chance for the Intel PRAM and NOR flash to go “head-to-head” soon albeit with PRAM making its mark using older generation litho tools.

Despite the talk of Intel mass production with Samsung and STMicro doubtless charging hard, an IBM paper may have the most interesting new technology to present. Details are sketchy to non-existent at this point regarding, “Novel Lithography-Independent Pore Phase change Memory.” It certainly sounds like the first NVM session will be worth attending to hear about this work along with Samsung’s.

In one of three plenary talks given at the 2006 International Electron Devices Meeting (IEDM), Dr. Chang-Gyu Hwang, president and CEO of Samsung Electronics’ Semiconductor Business, suggested that we are about to experience the largest semiconductor industry transition ever. Chip Shots and Physorg have more detailed accounts of this talk.

An entertaining Dr. Hwang predicted, “The approaching era of electronics technology advancement – the Fusion Era – will be massive in scope, encompassing the fields of information technology (IT), bio-technology (BT), and nano-technology (NT) and will create boundless opportunities for new growth to the semiconductor industry.” Dr. Hwang believes this long period of new growth will begin around 2010.

Bio-tech, health care, robotics, aerospace, solar cell, and environment-friendly R&D fields are expected to combine in critical ways to herald the dawning of the “New Era of Fusion Technology.” Semiconductor advancements will play a pivotal role in enabling this new trend, Dr. Hwang said.

“Unlike the paradigm shift from the personal computer to mobile and digital consumer applications, the introduction of massive-scale fusion technology – which represents the organic convergence of IT, BT and NT, will bring together a wide range of technology-related professions as the foundation for a new technology frontier,” Dr. Hwang said. “This historic new frontier will change the way we develop and harness semiconductor technologies in substantially improving the level of day-to-day convenience for consumers.”

“Commencement of the Fusion Era depends on the successful development of high-density, ultra-small, multi-featured semiconductor chips and multi-faceted, cross-industry solutions. To enter the new era, Dr. Hwang said it is essential to first overcome today’s limits in nano-technology.” You can see the rest of the SEC press release here.

It all sounds quite grand. Perhaps not for the company that set its sights on displacing Intel as the largest semi manufacturer. To-date at Samsung, the “Fusion” era belongs to memory. Once again, this should come as no surprise since Samsung has long dominated both DRAM and flash. But what does it have to do with multi-featured chips and cross-industry solutions?

Samsung’s first fusing exercise was the OneNAND. Not planning to be outdone, the phase-change memory unit shrunk the acronym from PCRAM to PRAM. Obviously, the explanation of PRAM from the corporation planning to dominate the industry was “Perfect RAM.”

The latest fusion device from Samsung is OneDRAM. As you might expect, this new device offers “better performance, with faster speed and lower power consumption and a lower chip count, with reduced area coverage on the printed circuit board.”

Taking nothing away from the technological achievements of the Samsung memories, it seems the One devices are more high density devices leveraging low cost processing to nibble at the edges of applications more typically using special-purpose memory.

Macronix recently announced that phase change memory (PCM) developed jointly with IBM and Qimonda had proven its viability below 20nm. The same DigiTimes article pointed out that this PCM technology proved it could overcome the ?physical barriers? currently inhibiting production of 65nm NOR flash.

These comments are puzzling considering SI has already completed a comprehensive analysis of Intel 65nm production NOR flash. Both detailed structural analysis and characterization of the individual FET dc performance suggest that NOR flash is performing very well at 65nm. Furthermore, Intel?s 65nm floating gate NOR flash was primarily a shrink of?Intel’s 90nm ETOX IX process that required little in the way of new materials or processes.

Although my colleagues and I are quite keen on PCM, it?s too early to put floating gate flash to bed. After all, we have also exhaustively studied a production 50nm NAND technology from the Intel-Micron partnership.

Above: Intel NOR Flash with floating gate space dimension of 65nm

Our preliminary analysis of the IM Flash Technologies’ 50nm 4Gb SLC NAND Flash unequivocally proves that it is, indeed, a 50nm device.  This moves IMFT to the head of the class in terms of the smallest process lithography.  Traditionally, it has been Samsung that has always pushed the process envelope, realizing 4Gb 65nm SLC NAND Flash in the first half of 2006.  Conventional wisdom was that this SLC-based strategy, and the corresponding process shrink, was starting to run out of steam.  However, IMFT has demonstrated that this is not necessarily the case with their 50nm solution.

This chip is quite an achievement for several reasons.  To start, this is the first actual device that our analysts have seen from the IMFT joint venture – a clear demonstration that this partnership is getting results.  Second, according to the 2005 ITRS Roadmap, the Flash Uncontacted Poly Si ½ Pitch (nm) should not be reaching 50nm until 2008.  This puts IMFT two years ahead of the ITRS schedule!

EETimes picked up details from our press release and put out an article titled “Intel, Micron trail Toshiba in flash density, says analyst”, which focused on the single level cell (SLC) and multi level cell (MLC) debate.  The article concentrated on the Mb/mm² comparison of the IMFT and Toshiba’s 8Gb 70nm MLC NAND Flash devices.  However, this is a bit like comparing apples and oranges, similar to a direct NAND and NOR comparison.  They are different implementations that accomplish the same end from an applications perspective.  If there is a solution with the required density that meets a company’s needs in terms of cost, performance, reliability, and size, then it is selected, whether it is a direct competitor or not.

The advantage of the IMFT solution is cost.  With a die size nearly 50% smaller than Toshiba’s, IMFT can produce about 50% more die per wafer.  The advantage of Toshiba is density.  By offering an 8Gb single die device, Toshiba can offer solutions for the increasing density demand of mobile consumer products.

Can IMFT continue to aggressively shrink the process lithography, enabling them to, in the near term at least, outpace competitors, even if they continue to use SLC technology while others migrate, or continue to produce, MLC?