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	<title>SemiSerious &#187; Memory</title>
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	<link>http://www.semiconductorblog.com</link>
	<description>Revealing commentary and news about the semiconductor industry.</description>
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		<title>IMFT 25nm NAND flash:  Seeing Double (patterning)</title>
		<link>http://www.semiconductorblog.com/2010/03/08/imft-25nm-nand-flash-seeing-double-patterning/</link>
		<comments>http://www.semiconductorblog.com/2010/03/08/imft-25nm-nand-flash-seeing-double-patterning/#comments</comments>
		<pubDate>Mon, 08 Mar 2010 13:00:08 +0000</pubDate>
		<dc:creator>Andrew Woodard</dc:creator>
				<category><![CDATA[Memory]]></category>
		<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/?p=491</guid>
		<description><![CDATA[It seems that a 25nm half pitch NAND flash process would have to use double patterning to defeat the limits imposed by the Rayleigh criterion.  In the self-aligned STI is proof that will have you seeing double.... patterning that is.]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2010/03/08/imft-25nm-nand-flash-seeing-double-patterning/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
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		<item>
		<title>Micron/Nanya 42nm predictions revisited</title>
		<link>http://www.semiconductorblog.com/2010/02/25/micronnanya-42nm-predictions-revisited/</link>
		<comments>http://www.semiconductorblog.com/2010/02/25/micronnanya-42nm-predictions-revisited/#comments</comments>
		<pubDate>Thu, 25 Feb 2010 13:00:36 +0000</pubDate>
		<dc:creator>Andrew Woodard</dc:creator>
				<category><![CDATA[Memory]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/?p=482</guid>
		<description><![CDATA[On February 8 I tantalized my audience (all two of you) with some guesses as to what UBM TechInsights would find inside the Micron/Nanya 42nm DDR3 SDRAM.  With the Detailed Structural Analysis almost ready for publication, I thought I&#8217;d go back and check my guesses, while also tipping my lucky readers with a few interesting [...]]]></description>
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		<slash:comments>1</slash:comments>
		</item>
		<item>
		<title>Micron/Nanya debut 42nm SDRAM</title>
		<link>http://www.semiconductorblog.com/2010/02/08/micronnanya-debut-42nm-sdram/</link>
		<comments>http://www.semiconductorblog.com/2010/02/08/micronnanya-debut-42nm-sdram/#comments</comments>
		<pubDate>Mon, 08 Feb 2010 15:57:02 +0000</pubDate>
		<dc:creator>Andrew Woodard</dc:creator>
				<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Memory]]></category>
		<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/?p=472</guid>
		<description><![CDATA[Seems like it was just last week (actually, 7 days ago to the hour) that Micron was unveiling its newest, smallest NAND flash process to date. This week, they’re at it again:  Jointly developed with Nanya, the 42nm 2Gb DDR3 SDRAM, with a 49.2mm2 footprint, packs 41.6 Mb into each square millimeter. Having just had [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2010/02/08/micronnanya-debut-42nm-sdram/feed/</wfw:commentRss>
		<slash:comments>1</slash:comments>
		</item>
		<item>
		<title>NAND flash frontier reaches 25nm thanks to Intel, Micron</title>
		<link>http://www.semiconductorblog.com/2010/02/01/nand-flash-frontier-reaches-25nm-thanks-to-intel-micron/</link>
		<comments>http://www.semiconductorblog.com/2010/02/01/nand-flash-frontier-reaches-25nm-thanks-to-intel-micron/#comments</comments>
		<pubDate>Mon, 01 Feb 2010 16:00:52 +0000</pubDate>
		<dc:creator>Andrew Woodard</dc:creator>
				<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Memory]]></category>
		<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/?p=467</guid>
		<description><![CDATA[IMFT, the flash memory joint venture between Intel and Micron, announce today that they are sampling 25nm 2-bit-per-cell NAND flash devices in densities up to 64Gb (167mm2).  In doing so they become the current “kings of the mountain” with bragging rights on bits per mm2 (392Mb/mm2) and finest line pitch in a launched product.  They [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2010/02/01/nand-flash-frontier-reaches-25nm-thanks-to-intel-micron/feed/</wfw:commentRss>
		<slash:comments>1</slash:comments>
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		<item>
		<title>MISFETs at VLSLI 2009</title>
		<link>http://www.semiconductorblog.com/2009/06/14/misfets-at-vlsli-2009/</link>
		<comments>http://www.semiconductorblog.com/2009/06/14/misfets-at-vlsli-2009/#comments</comments>
		<pubDate>Mon, 15 Jun 2009 03:22:20 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Event Coverage]]></category>
		<category><![CDATA[Game consoles]]></category>
		<category><![CDATA[ITRS]]></category>
		<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Memory]]></category>
		<category><![CDATA[Process]]></category>
		<category><![CDATA[16nm]]></category>
		<category><![CDATA[Ge MISFET]]></category>
		<category><![CDATA[High-K]]></category>
		<category><![CDATA[HKMG]]></category>
		<category><![CDATA[intel]]></category>
		<category><![CDATA[Toshiba]]></category>
		<category><![CDATA[VLSI Symposium]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/?p=331</guid>
		<description><![CDATA[

I mentioned elsewhere that Intel&#8217;s approach of removing the oxide interlayer prior to high-K dielectric deposition was a significant advance on the road to scaling HKMG processes for the 16nm node.  This  joint effort with Sematech and UT Dallas will be presented at VLSI Technology Symposium 2009. Intel&#8217;s oxide-less gate stack technique might be signaling [...]]]></description>
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		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Insight Awards Selections</title>
		<link>http://www.semiconductorblog.com/2009/03/04/insight-awards-selections/</link>
		<comments>http://www.semiconductorblog.com/2009/03/04/insight-awards-selections/#comments</comments>
		<pubDate>Wed, 04 Mar 2009 12:48:49 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Events]]></category>
		<category><![CDATA[Memory]]></category>
		<category><![CDATA[Process]]></category>
		<category><![CDATA[Semiconductor Insights]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/?p=243</guid>
		<description><![CDATA[This week marks the beginning of the long and sometimes arduous process of selecting winners in the SI Insight Awards in each of the technology categories. Of course, these are:

Process Technology
Non-volatile Memory
DRAM
Mobile Processor

Of course, it&#8217;s always a treat to talk to the creators of technology about their products. Sometimes, it&#8217;s more like listening to proud [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2009/03/04/insight-awards-selections/feed/</wfw:commentRss>
		<slash:comments>2</slash:comments>
		</item>
		<item>
		<title>Flash Forward to Toshiba&#8217;s High-K</title>
		<link>http://www.semiconductorblog.com/2008/10/24/flash-forward-to-toshibas-high-k/</link>
		<comments>http://www.semiconductorblog.com/2008/10/24/flash-forward-to-toshibas-high-k/#comments</comments>
		<pubDate>Fri, 24 Oct 2008 20:23:54 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Memory]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2008/10/24/flash-forward-to-toshibas-high-k/</guid>
		<description><![CDATA[Toshiba is the first flash manufacturer to incorporate a high-K dielectric in their product. Their innovative inter-poly dielectric has allowed Toshiba to scale their floating gate flash memory to 43nm. The 16Gbit multi-level cell (MLC) device from Toshiba sets the new high watermark for NAND flash bit density at 139Mbits/mm².
Samsung claimed the first implementation of high-K [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2008/10/24/flash-forward-to-toshibas-high-k/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Enough Already</title>
		<link>http://www.semiconductorblog.com/2008/08/18/enough-already/</link>
		<comments>http://www.semiconductorblog.com/2008/08/18/enough-already/#comments</comments>
		<pubDate>Mon, 18 Aug 2008 21:30:23 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Event Coverage]]></category>
		<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Memory]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2008/08/18/enough-already/</guid>
		<description><![CDATA[For years the question, “How much is enough?” has been debated regarding NAND flash endurance. How many write cycles do you really need over the lifetime of a camera card or memory stick? How long do you need your portable data to stay intact?
SI’s senior memory analyst, Young Choi, attended the recent Flash Memory Summit [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2008/08/18/enough-already/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Embedded RAM</title>
		<link>http://www.semiconductorblog.com/2008/01/31/embedded-ram/</link>
		<comments>http://www.semiconductorblog.com/2008/01/31/embedded-ram/#comments</comments>
		<pubDate>Thu, 31 Jan 2008 16:46:49 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Game consoles]]></category>
		<category><![CDATA[Memory]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2008/01/31/embedded-ram/</guid>
		<description><![CDATA[For years, there has been speculation that traditional SRAM would be replaced with a denser type of memory for SoC devices. In fact, TI once announced that they would use ferroelectric RAM or FeRAM beginning at 90nm for their devices. Fear of ever-worsening process variability has been widespread. Alas, we have entered the 45nm period, [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2008/01/31/embedded-ram/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>VLSI &#8211; DRAM Technology</title>
		<link>http://www.semiconductorblog.com/2007/05/09/vlsi-dram-technology/</link>
		<comments>http://www.semiconductorblog.com/2007/05/09/vlsi-dram-technology/#comments</comments>
		<pubDate>Wed, 09 May 2007 20:14:49 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Events]]></category>
		<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Memory]]></category>
		<category><![CDATA[Process]]></category>
		<category><![CDATA[Uncategorized]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/05/09/vlsi-dram-technology/</guid>
		<description><![CDATA[With the VLSI Syymposia just a little over a month away, I will wrap up my picks for papers to watch for by looking at DRAM. For the Technology Symposium, Samsung is over-represented with five out of the seven presentations split between two sessions.
Two of Samsung&#8217;s articles will discuss aspects of their FinFET DRAM cell, [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2007/05/09/vlsi-dram-technology/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>VLSI 2007 &#8211; Phase Change Memory Technology</title>
		<link>http://www.semiconductorblog.com/2007/04/17/vlsi-2007-phase-change-memory-technology/</link>
		<comments>http://www.semiconductorblog.com/2007/04/17/vlsi-2007-phase-change-memory-technology/#comments</comments>
		<pubDate>Tue, 17 Apr 2007 21:49:25 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Events]]></category>
		<category><![CDATA[Memory]]></category>
		<category><![CDATA[Process]]></category>
		<category><![CDATA[Uncategorized]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/04/17/vlsi-2007-phase-change-memory-technology/</guid>
		<description><![CDATA[This is my second review of papers to be presented at the VLSI Technology Symposium. Today, I will take a look at the most promising papers on phase change memory technology (PCM or PRAM). Today at its spring development forum in Beijing, Intel announced that it will produce a 128M 90nm PRAM later this year. This is bound to create some extra buzz [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2007/04/17/vlsi-2007-phase-change-memory-technology/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Fusion Memory</title>
		<link>http://www.semiconductorblog.com/2007/03/20/fusion-memory/</link>
		<comments>http://www.semiconductorblog.com/2007/03/20/fusion-memory/#comments</comments>
		<pubDate>Tue, 20 Mar 2007 20:12:59 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Memory]]></category>
		<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/03/20/fusion-memory/</guid>
		<description><![CDATA[In one of three plenary talks given at the 2006 International Electron Devices Meeting (IEDM), Dr. Chang-Gyu Hwang, president and CEO of Samsung Electronics&#8217; Semiconductor Business, suggested that we are about to experience the largest semiconductor industry transition ever. Chip Shots and Physorg have more detailed accounts of this talk.
An entertaining Dr. Hwang predicted, “The approaching [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2007/03/20/fusion-memory/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Intel 65nm NOR StrataFlash</title>
		<link>http://www.semiconductorblog.com/2006/12/12/intel-65nm-nor-strataflash/</link>
		<comments>http://www.semiconductorblog.com/2006/12/12/intel-65nm-nor-strataflash/#comments</comments>
		<pubDate>Tue, 12 Dec 2006 17:35:30 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Memory]]></category>
		<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/?p=7</guid>
		<description><![CDATA[
Macronix recently announced that phase change memory (PCM) developed jointly with IBM and Qimonda had proven its viability below 20nm. The same DigiTimes article pointed out that this PCM technology proved it could overcome the ?physical barriers? currently inhibiting production of 65nm NOR flash.
These comments are puzzling considering SI has already completed a comprehensive analysis [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2006/12/12/intel-65nm-nor-strataflash/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>SLC v. MLC Flash Memory: Comparing Apples and Oranges</title>
		<link>http://www.semiconductorblog.com/2006/08/22/slc-v-mlc-flash-memory-comparing-apples-and-oranges/</link>
		<comments>http://www.semiconductorblog.com/2006/08/22/slc-v-mlc-flash-memory-comparing-apples-and-oranges/#comments</comments>
		<pubDate>Tue, 22 Aug 2006 20:12:41 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Memory]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2006/08/22/slc-v-mlc-flash-memory-comparing-apples-and-oranges/</guid>
		<description><![CDATA[Our preliminary analysis of the IM Flash Technologies’ 50nm 4Gb SLC NAND Flash unequivocally proves that it is, indeed, a 50nm device.  This moves IMFT to the head of the class in terms of the smallest process lithography.  Traditionally, it has been Samsung that has always pushed the process envelope, realizing 4Gb 65nm SLC NAND [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2006/08/22/slc-v-mlc-flash-memory-comparing-apples-and-oranges/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Freescale MRAM &#8211; an in-depth examination</title>
		<link>http://www.semiconductorblog.com/2006/08/08/freescale-mram-an-in-depth-examination/</link>
		<comments>http://www.semiconductorblog.com/2006/08/08/freescale-mram-an-in-depth-examination/#comments</comments>
		<pubDate>Tue, 08 Aug 2006 14:45:24 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Memory]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/08/08/freescale-mram-an-in-depth-examination/</guid>
		<description><![CDATA[Once promised as the replacement to conventional non-volatile memory, the prospects around MRAM are no longer as clear. Only two vendors have succeeded in bringing MRAM parts to the mass market &#8211; Cypress and Freescale. That said, Cypress discontinued their offering shortly after release and Freescale, which announced MRAM back when they were still known [...]]]></description>
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		<slash:comments>0</slash:comments>
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