SemiSerious

This week presented interesting news as two image sensor technologies I thought might one day displace traditional types appear to have made breakthroughs on the march to commercialization. NHK showcased an active layer over IC - or AIC -type of sensor while OmniVision announced they would be sampling a backside illuminated - BSI - detector next month. Junko Yoshida’s detailed article on EETimes put me onto the backside scent. 

For the traditional CMOS image sensor (front-side illuminated or FSI to use the OmniVision convention), the ratio of stack height or optical path length to pixel pitch is an important limitation. There are many drivers - both market and technical - for decreasing the pixel pitch of the image sensor. Leaving those aside for now, shrinking active pixel sensor dimensions is a given. Since the active silicon region (or photodiode) where incoming light is converted into electrical energy sits at the bottom of the metal interconnect, it’s easy to see why this dimension receives so much attention. As a result image sensor manufacturers have raced to reduce the height of the interconnect over the photodiode. This is most important with CMOS image sensors (CIS) since CCD’s do not include any processing circuits on the sensing chip. CIS devices often incorporate a great deal of signal processing on the same silicon as the sensor. Increasing integration drives more metal wiring levels if you hope to keep the total chip size under control.

About the time SoC integration on CIS was reaching a peak, a few manufacturers transitioned from aluminum to copper for the interconnect. Copper’s lower resistance allows thinner wires for a given line pitch for the same design target resistance as aluminum. Thinner metals means a shorter optical path to the photodiode. But copper integration is not ideal for image sensors since the barrier levels create unwanted interfaces resulting in reflections and optical system losses. There were also rumours of lower camera module yields for devices built with copper. Whatever the reasons, many manufacturers returned to aluminum and longer optical paths. But a few percent improvement will not eliminate the issues with optical path length, something these two new technologies avoid for the most part.

Both AIC and BSI approaches treat interconnect where it should be - literally the “back end” from the optical point of view. An AIC detector adds active silicon with photodiodes on top of the chip wiring, so light reaches it first. BSI flips the chip allowing light to hit the sensor from the back. Viewing a BSI detector in cross-section, it would like very similar to the traditional FSI device. The only differences is that light enters through the backside of the substrate opposite to the active silicon surface.

Several companies have published work on the AIC approach. The sensor in these cases is most commonly amorphous silicon patterned into detectors after traditional BEOL metal IC processing. These devices employ similar structures and materials to those used in LCD display panels. ST Micro and Samsung have been brewing this type of technology for a while. (ST and Samsung both had multiple presentations at IISW 2007. See my earlier post.)

But the NHK sensor uses an organic light sensitive layer rather than silicon. I have not been able to confirm a connection with FujiFilm, but this sounds a lot like the technology they presented at last year’s IISW. It doesn’t take too much imagination to visualize the organic sensor approach as spreading old school analog film emulsions over a state-of-the-art readout IC.

I guess it’s obvious that substrate processing must be adapted for the BSI device. That is almost assuredly based on SOI technology. The leading SOI substrate provider is Soitec. CEA-LETI spawned another company in the SOI space in 2003. Tracit Technologies offers layer transfer technology to IC’s onto SOI substrates. Last year, they helped e2V bring backside detectors to the “medium volume professional image sensor market.” I think TraciT will be an important factor in getting BSI into the high volume consumer market.

There has been a lot of news this year about the wafer-level camera (WLC) and through-silicon vias (TSV) to facilitate it. Even some reverse engineering blogs have something to say about TSV! BSI offers an interesting packaging option in addition to the many performance advantages as well. It lends itself well to flip-chip packaging. Perhaps the cost adders that have maligned the BSI approach in the press will be more than compensated by the cheaper flip chip packaging it will allow.

OVT now calls this technolgoy “BSI” for back-side imager, but it seems to have been previously called “BID” as I learned at IISW 2007. Dr. Bedaprata Pain should now be very happy that his attempts to jump-start the transition to back-side illumination may have sparked commercialization of the technology.

OmniVision’s PR states:

OmniBSI architecture delivers a number of performance improvements over FSI, including increased sensitivity per unit area, improved quantum efficiency and reduced cross talk and photo response non-uniformity, which all lead to significant improvements in image quality. Since light directly strikes the silicon, the fill factor of the image sensor is significantly improved so as to deliver best-in-class low-light sensitivity. A much higher chief ray angle enables shorter lens heights which in turn allows for thinner camera modules, which are ideal for use in the next generation of ultra-thin mobile phones. Finally, BSI technology affords a much larger aperture size, which allows for lower f stops facilitating the development of better performing camera modules with superior camera performance.

Even though this is written by the spin doctors, their statements are absolutely correct. The improved low-light sensitivity will be especially important for cameraphones as users, and therefore designers, are demanding improvements to images acquired in pubs, restaurants and parties. Nokia made this very clear at Image Sensors Europe, and those sentiments were echoed by a number of sensor manufacturers including Aptina and OmniVision.

As for the suggestion that there is little novelty to the BSI detector approach, I can’t argue that the idea was around for a while (check Stern, Proc. SPIE, vol. 1071, 1989). For example, MIT Lincoln Labs has a long history in this field. But then again, how long did it take the laser to make its way into a useful consumer product?

A couple of my colleagues were surprised to say the least this week when the devices they were working on turned out to be rather elaborate fakes. Or not - I’m not exactly sure.

SI was undertaking a reverse engineering project looking at a certain leading CMOS image sensor supplier’s device who is known to use a certain leading Asian fab to manufacture its devices. Ten units of the chip came from a parts distributor in Hong Kong.

At first glance, the devices appeared as expected. The package was standard-issue for image sensors with hermetically-sealed cover glass over the sensor die. Everything still appeared normal after removing the sensor die from the package. A typical SoC type of image sensor layout was clear with the pixel array occupying about 26% of this 38 square millimeter chip.

But that’s where our expectations diverged from reality.

After dropping one die into acid to remove all the interconnect layers and get a quick look at the active area patterning, the silicon appeared blank. The engineer then quickly beveled the IC in order to expose all of the active layers. Again, there was only whitespace deeper into the chip. Starting with yet another sample from the lot, our lab cross-sectioned through the device. This final step revealed only one metal level, color filter array, and microlenses - no transistors or lower levels of metallization.

A senior process engineer not assigned to the project suggested these devices could be mechanical samples. That seemed reasonable. If you wanted to test a new package type for instance, it might make sense to order a few duds built with only the BEOL processes. Even more believable would be a BEOL-only device for environmental testing since microlens arrays are notoriously sensitive to high temperatures. Increasing adoption of imagers into the automotive industry along with research reports of temperature-hardened microlenses adds some credibility to this idea. (For example, see a TI Japan and Tohoku University paper from IISW 2007 entitled, “A Wide Dynamic Range CMOS Image Sensor with Resistance to High Temperatures.”)

However, the devices we bought were not advertised as mechanical samples but as fully operational image sensors under a leading manufacturers part number. And it wasn’t just one or two devices. The whole lot of 10 appears to suffer the same lack of active circuitry. The distributor is from China, so I know what many of you are thinking - another counterfeit chip scandal is brewing. There’s been a lot made of counterfeiting activity in China. A quick search of that keyword at EETimes will give you dozens of stories to choose from if you want to dive deeper into this murky field.

My best guess at what happened in the present case is that a legitimate order was placed for mechanical samples. But a few “extras” were produced beyond what was required for the environmental testing. Some enterprising worker at the manufacturer decided not to waste the spares and found a discount IC distributor on the lookout for cheap devices.

The first step to uncovering a more complex scandal would be to identify the IC foundry of origin. I happen to know some engineers who have a lot of experience in this field. If they are able to determine that these devices were produced at one of the expected manufacturers main production lines, then the mechanical sample overrun theory would be supported. If not, then maybe this will be the beginning of a bigger story of a semi-serious counterfeiting operation based on chips that could pass only an external visual inspection. Was it was an outfit that only managed to steal one layers worth of design files? Or maybe someone reverse engineered only one level of a legitimate version of this manufacturers device.

This isn’t the first strange case I’ve seen of a partially processed, yet fully packaged chip getting into the distribution channel. It’s unfortunate my memory is so bad that I can’t remember more details of that device which is now buried somewhere deep in the Semiconductor Insights chip graveyard. What I do remember is similar though. Despite containing all the interconnect levels, the polysilicon was an unpatterned, featureless sheet, and there were no vias between metal lines. I guess we weren’t as focussed on counterfeit in those days because it never occurred to me at the time.

My conspiracy theory is that the bean counters took over the fab. Maybe this is the “New Economics of Semiconductor Manufacturing” as described in IEEE Spectrum. Why not save a couple bucks by just avoiding those costly front-end manufacturing steps altogether? After all, with image sensor ASP’s getting continuously hammered, what else can manufacturers do to keep making a buck?

This article originally appeared in EETimes Under the Hood. Unfortunately, there was an editing hiccup, so I have decided to post the complete text of the original article here. -Ed 

Two months after Semiconductor Insights provided the first public view of Intel’s 45nm technology and nearly a month after Intel’s IEDM presentation, it seems appropriate to revisit both the technology itself and what Intel was willing (and perhaps less willing) to reveal about it.

As noted on EETimes almost one month prior to the 2007 IEDM, the main features of Intel’s 45-nm technology are the incorporation of high-k hafnium-based dielectric material, titanium nitride (TiN) for the PFET replacement gate, and a TiN barrier alloyed with a work function tuning metal for the NFET replacement gate.

Although not the first 45nm node technology available on the open market, Intel’s process is the first to incorporate high-k metal gate (HKMG) technology. Panasonic (Matsushita) was actually the first to the 45nm node with an ASIC-optimized process using traditional polysilicon gates with SiON dielectrics.  This process is designed for density over performance and probably more indicative of the direction most manufacturers will be heading at 45nm. Density is certainly the key for the Panasonic process as it boasts several critical dimensions smaller than Intel’s.

Some high points of Intel 45nm HKMG technology are:

• High-k first, metal gate last integration
• Hafnium oxide (HfO2) gate dielectric (1.0nm EOT)
• Dual band edge workfunction metal gates
• TiN for PMOS
• TiAlN for NMOS

The gate last integration is one point that needs a bit of clarification in the Intel process flow.
Process Integration

Polysilicon gates may be gone in the final Intel 45nm products, but they are far from forgotten. A great deal of the transistor formation still depends on the polysilicon techniques that have dominated the industry for the last 40 years. In fact, the references to “first” and “last” refer to the order of the high-k and metal gate formation with respect to the polysilicon deposition.

It is now well-known that Intel uses a gate last or replacement gate process flow at 45nm. But there is an opportunity for a great debate of the semantics of the terms, whether it’s “gate” or “last.” I’m not predicting that the lawyers are already on their way, but there’s bound to be a patent out there that will create just such an argument.

The replacement gate flow allows Intel to reuse many process steps and tools from the age-old polysilicon gate technology. Patterning polysilicon and forming traditional silicon oxide and nitride sidewall spacers leverages tried and true self-aligned processes for source and drain formation and their lightly doped extension regions. Once these steps are completed, the polysilicon is removed and workfunction metals are deposited in their stead.

But there is something interesting going on even before the first poly deposition. Contrary to the suggestion in their IEDM paper, Intel deposits the first workfunction metal prior to the sacrifical gate polysilicon. For the P-channel transistor, titanium nitride (TiN) is deposited immediately after the HfO2 dielectric. Adding aluminum to form TiAlN tunes the workfunction for the N-channel transistors. There are a couple of ways to get the aluminum into the NFET’s gate, but I will not mention those here. In general terms, these primary workfunction metals are blanket deposited in their associated conductivity regions on the die.

Intel’s process protects HfO2 from the polysilicon etch by depositing the first workfunction layers before forming and patterning polysilicon. SI engineers refer to the first gate metal layer as the top interface layer (TIL) because of the undeniable protection it provides the HfO2 dielectric. The P-type metal gates are TiN while Al is added to create TiAlN and the appropriate workfunction for NMOS. Thicker layers of both metals are deposited in their respective N- and P-channel transistors after removing the sacrificial polysilicon and a barrier layer is formed on the bottom and sidewalls of the trench left behind by the polysilicon etch.

Making a final determination about whether the first or second layer of the workfunction metals is the most important in the Intel device would require additional mathematical treatment or computer simulations which are beyond the scope of this article. Is the primary gate the metal layer deposited before polysilicon or the one that comes after? To be fair, no one expects manufacturers to publicly disclose specific details of their processes. Either way, comments about the meaning of “gate” are arguably less important than the electrical performance of the finished product. Intel 45nm technology is certainly impressive in that regard. SI’s extraction of transistor electrical parameters indicates the following saturated drive currents at 1.0V and room temperature:

• PFET IDSAT = 1.08mA/µm
• NFET IDSAT = 1.36 mA/µm

Intel confirmed these values at their IEDM presentation in December (although our PFET number is actually 10µA higher than Intel reported). Not surprisingly, our results show higher drive currents at low temperature (-20°C) and reduced current at high temperature (85°C).

These high values for drive current evoke more questions regarding the gate structure. There has always been a discrepancy between the physical gate length, LG, of transistors and the shorter electrically active channel length, Lelec. But before the advent of modern metal gate technology, it was relatively easy to specify LG and compare transistor performance between fabs. The Intel gate structure creates some new problems for analysts.

Intel reports a gate length of 35nm which fits well with the 1.36mA/µm drive current generated by their NFET. However, the edge-to-edge dimension of their gate structure is closer to 45nm if measured in a fashion similar to the standard used for polysilicon gates. So what gives? The ratios of LG, Lelec and source/drain extension lengths would be out of whack to produce such large saturation currents.

The answer appears related to the question about the location of the metal gate’s edge. In the past, it was assumed that the entire width of the poly gate influenced carriers in the transistor channel. Since polysilicon is etched and replaced with a metal gate filling the trench in the gate last process, the situation is less straightforward. The first material deposited into the gate trench is not metal for the gate, but actually a barrier material, so the active portion of the gate is less than the traditional length measurement that would essentially run between the sidewall spacer on either side of the gate. The barrier is quite thin, though, so that would not account for the gate measurement difference.

What appears to set the electrically active gate length is the bird’s beak formed where the sidewall spacer meets the TIL. SI analysis concluded that this bird’s beak is the result of TIL and high-k etches undercutting the polysilicon. Re-oxidation of the polysilicon sidewall prior to silicon nitride spacer formation exacerbates the undercut. For the metal gate deposited into the trench, there is a thick, relatively low-k path toward the channel at this point that obviously could not electrically influence charge carriers in the region directly underneath the bird’s beak.

The critical portion of the metal gate could also be the TIL itself. Since this layer is composed of the same workfunction metal as the gate last layer, perhaps its edge defines the metal gate length. Fortunately, the edge of the TIL layer approximately aligns with the bird’s beak above it, so the choice of measurement point will not affect the value you get for LG.

The punch line to all of this is that the gap between gate trench edge and the electrically active edge of the workfunction metal (whether first or last) accounts for somewhere between 8 and 10nm. And that appears to explain the difference between Intel’s reported value for LG and what the rest of us have been looking at.
 
Despite its cure for leakage power, adding hafnium creates new headaches for the process integration engineer. Intel avoided hafnium’s downsides – threshold voltage pinning and reduced carrier mobility – by creating a silicon oxide (or possibly oxynitride) bottom interface layer (BIL) between the silicon substrate and the HfO2 layer. The BIL not only gets hafnium into the gate stack, it also gives the process engineer one more tuning knob. Since the gate dielectric’s influence on the transistor channel and electrical performance is a function of the individual contributions of the various layers, threshold voltages can be controlled by varying the BIL thickness for different transistor applications.
DFM

Process variability and designing for it are now hot topics as problems like line edge roughness and random dopant fluctuations become more problematic at 45nm.  This was addressed in Intel’s second presentation at IEDM 2007. Kelin Kuhn discussed improving yield by process improvements as well as design changes. The SRAM cell illustrated Kelin’s point as she showed the evolution from 90nm to 45nm design. The “tall” cell layout used at 90nm was replaced with a “wide” cell at 65nm.  The 65nm wide SRAM cell design improved dimension control and variability by aligning the polysilicon in a single direction and removing the corners in the active area patterns. At 45nm, Intel’s process removed “dog bone” and “icicle” shapes by employing only square end caps. These uniform structures are also easier to fill reliably in the gate last process.

Intel continues to use 193nm dry lithography at 45nm. Restricted design rules create “structured” gate layouts as Dr. Kuhn mentioned in her discussion of the SRAM cell. This DFM technique of uniform, regular arrangement of metal gates improves yields for the advanced HKMG technology without investing in new immersion tooling. Creating strictly rectangular gate patterns did require an extra step as double-patterning was used for the sacrificial polysilicon layer.

Many features of Intel’s 65nm process remain in evolved form. “Third-generation” strained silicon is used which is structurally similar to the embedded SiGe PMOS of their 65nm process. Nickel-salicide is also used again at 45nm. Intel employs dual damascene copper up to metal nine. SiCN barrier with carbon-doped oxide (CDO) create the low-k inter-level dielectric integration scheme.

Final Thoughts

However you slice it (pun intended), the Intel process is truly innovative. For technology analysts and pundits, it brings something fresh to the discussion –Moore’s (never-ending) Law, future trends, scaling and arguments about how they did it.

I want to thank Fayez Elchamaa, Vu Ho, Xu Chang and the rest of the crack Intel 45nm project team for their hard work. The SI analytical team has managed to piece together a large and complex set of data in order to provide both this brief overview along with the detailed analysis available to our clients.

Today Laura Peters from Semiconductor International (the other SI) hosted a webcast providing an overview of the contents of the upcoming 2007 Edition of the Semiconductor Industry Association’s (SIA) roadmap for technology - the ITRS. If there is anyone who really knows what’s in that upcoming document, it is Intel’s Alan Allan, and he gave the presentation. It’s the second time I’ve had the chance to listen to this Intel guru (see first time, here). This time Allan focused his thoughts on diversification of the ITRS to “more than Moore.” Scaling and Moore’s Law have been the rails for the semiconductor industry since its early days, but there is only so much that physical scaling can do and some places it’s just not at home.

The most obvious technology that gives us more without Moore is MEMS. Micro (or nano) electromechanical systems (MEMS) are at the heart of many systems from air bag deployment to Nintendo Wii game controllers. For Alan Allan and other industry luminaries, turning their attention to the critical part of consumer electronics systems to where the rubber meets the road is part recognition of the importance of the overall system or product and part realization that many aspects of scaling are creating more trouble than they are worth. Those troubles include increasing power consumption and capital consumption to get a cutting-edge chip designed, fabbed and into the market.

Sensors and actuators, or the way microelectronics actually interacts with our physical world, are a critical aspect of everything in our new digital age. Portable music players are ubiquitous primarily because of digital representation and storage of content, but they still need to drive something that can render an analog signal (that’s sound to a headphone if that last bit was too obtuse). You can add as much digital signal processing horsepower you want to a car, but it isn’t going to detect and correct a skid if there isn’t an analog detector at the front end of the signal path. And sensors - in particular MEMS devices - have no need for the latest lithography or the fastest transistors. MEMS technology is most at home in older, sometimes fully depreciated fabs.

Most of the “more than Moore” diatribe above is my own. I apologize and reward you for reading this far with a couple of comments made by the other ITRS representatives who were on hand for answering questions at the webcast. These actually relate more to Moore and traditional scaling issues.

When will EUV be ready? Will Conley, one of Freescale’s members of the lithography working group, answered that the next generation of litho will be ready for 22nm but not before. As for nanoimprint, he said this will only be used for “early device learning” until throughput can be improved.

I took note of a couple of other questions about interconnect. Chris Case (of the Linde Group) said there would not be a “materials” solution to inter-level dielectric constant below 2.0. He quickly added that there will be an air gap combination approach to get below k=2.0. Alan Allan also addressed the slowing of reductions in effective k values and many unresolved problems in technologies that are getting closer to their required introduction date (red brick wall for 2012). Chris Case also pointed out that 3D interconnect technology is well-proven in development fabs and will be ready when the industry is ready to take the plunge.

Okay, so this post is a day after the news, but that’s still better than posting beforehand to create the appearance of a scoop. Yesterday, Intel’s much anticipated presentation of their 45nm process was held at IEDM in Washington. Although I suggested last week that Intel would reveal certain details of their process, much of it still remains a mystery to the wider public. Of course, the devices are openly available allowing one to actually see what’s inside. The IEDM paper gives many details about staying on the curve (Moore’s Law, that is) and the transistor performance the 45nm HKMG process achieves. But it’s more than a little short on details of how that performance is enabled. Anyone fortunate enough to analyze one of the Penryn chips could even conclude that Intel was hoping to throw us all off the scent. (I apologize too since my Perler bead model in the photo is also a bit misleading.)

Intel describes the transistor formation as “high-k first and metal gate last.” If last means after sacrificial poly, then that description is not entirely accurate.

But IEDM offers more than the Intel 45nm show. This was even evident even to Popular Mechanics’ blogger who noted that Intel 45nm would be “duelling” with the AMD, IBM, Freescale, Sony and Toshiba announcement about 32nm. I appreciate, though, the fact that neither the “duel” or Intel’s 45nm presentation itself obscured some more futuristic technology for at least this one reporter in DC. Check Popular Mechanics for some pictures and description of Stanford and Bosch spiral sensor arrays and the University of Tokyo “communications sheet” that allows devices placed on it to communicate with one another while receiving power for charging (also on TR today.

As an IEDM outsider this year, I picked the energy harvesting devices session (14) as a must see. Running parallel to the CMOS technology platform session, I’m sure that it was largely overshadowed by the big boys. But many of these concepts will benefit humankind in a variety of ways and arguably more than CMOS IC technology. As most will guess, the harvesting session includes photovoltaics or solar cell technology, one of the hottest and most newsworthy topics of the last year in the semiconductor industry.

Everybody knows about oil crises, global warming and the Kyoto protocol, so alternate energy is really a topic for the mainstream news channels. But micro- and nano-power generation is where it’s at. Or I guess I should say where it will be at. Check some earlier posts to SemiSerious to track down some information in this exciting field. I really think this will be field that enables many amazing devices from multipurpose nanobots in your bloodstream to wide area sensor nets keeping tabs on the population for the large sibling.

At the Common Platform Technology Forum last month, the design for manufacturing (DFM) session message was, “not if but when the industry will have to move to structured gate layouts.” Intel already has.

The industry is at a point where design for variability (DFV) is required. The old approach would be to add margin, but design margining has no scalability and no future.

A better option is to take a DFM approach that creates more litho-friendly designs. Intel has pushed out investment in new lithography tools, keeping their 193nm dry toolset at 45nm. Surely, one outcome of that decision was a requirement to use restricted design rules or a “structured” gate layout to improve yields. There is tangible evidence of this on the Penryn die. The metal gate lines are patterned in regular, parallel patterns to improve both printability and processing to maintain fidelity of the final structures. CMP is obviously a critical step in Intel’s gate last approach, and the structured layout also improves CMP. Filling the narrow trenches with the metal gate material must be easier too when there are fewer nooks and crannies in nice straight gate lines.

In an effort to maintain control of the message as information begins to leak out just before their IEDM presentation on Tuesday, Intel’s Kaizad Mistry provided a few nuggets to Semiconductor International. By restricting design rules to keep poly lines running in a single direction and switching to a wider SRAM architecture, Intel was able to push its SRAM feature size harder, Mistry said, adding that, “Many times, these design changes are beneficial for patterning.”Semiconductor International reports that Intel used double patterning lithography to “square off the ends of the patterns, reducing rounded ends (dogboning) and irregular shapes (icicles).” Looking at the Penryn deprocessed to tungsten metal 1, it is easy to compare the double-patterning used at the metal level to the tungsten trenches where it was not. According to Mistry, “There are benefits in terms of performance and layout density. The trench contact serves as a form of what you might say is local interconnect. And in terms of patterning, it is easier to pattern lines and spaces than a field of holes.”

I’m sure it’s not intentional, but the PMOS image released by Intel is a little misleading. At their paper on Tuesday at IEDM, look for Intel to clarify the situation by showing that the real story of their metal gate is much closer to the hafnium oxide high-k layer.

MIT Technology Review ran a very interesting story about printable electronics this week. Kovio, a company spun out of MIT’s Media Lab, announced a new process for printing transistors with inkjet printing techniques. According to this report, Kovio may begin production with disposable smart cards for public transit. Performance of Kovio devices will be better than what has been reported to date for IC’s created with commercial printing technology. The reason is that Kovio is the only group known to be applying this approach to inorganic materials.

Technology Review predicted several products for printed electronics including RFID tags and very large, full wall type displays. For a real potential boost to RFID adoption for inventory control, TR suggests that the cost of making an RFID tags this way could dip well below five cents.

But SI Senior Scientist, Dr. Ray Haythornthwaite, made these predicitions more than five years ago. In a report that was too early for its time or our sales force, Ray had already predicted electronic “wallpaper” that would change according to your mood or desire for instant redecorating. (Satisying my wife’s interior design whims would be so much easier if this product was available today.) The landmark, An Examination of Current Developments and Future Directions of Organic Semiconductor Technology (March 2002), provided a thorough examination of the early research into organic electronics and predicted the future for the technology. Everyone is still looking forward, but the field seems to be inching closer to making some real products.

Perhaps the killer app for ink-jet IC printing is the RFID tag. Ray also foresaw this as an obvious use for this technology. His rationale was that the packing box was there anyway, space was not (usually) at a premium. Why not just spray it on? Oddly enough, this outside-the-box thinking came at a time when our own spin-off company, Symagery Microsystems, was trying to break into the 2D barcode space. The transitioning of barcodes from 1D to 2D was evolutionary. The idea of printing a smart RFID tag to completely replace the barcode was certainly revolutionary. Ray is now retired from Semiconductor Insights but is available part-time for consulting in the semiconductor field. I don’t want to put his email here for spambots, but he is not hard to find on the web (not many Haythornthwaites in my phone book anyways).

Perhaps we can coin a new term in this nanotech era - millitech for millimeter-scale electronics. Using the ubiquitous ink-jet reverses some other trends - maybe even Moore’s Law. Millitech scaling trends and large scale integration would refer to ever-larger circuits covering more available real estate. This may put technology into the hands of ordinary people in contrast to the evermore exclusive club of megacorporations that can afford to build billion dollar wafer fabs. Consider one San Francisco artist who attempted to use nanobots as a form of high-tech graffiti, littering the little electronic insects around. Why not stick to a more traditional style of the art using spray cans? Different colors are replaced by the various transistor building materials, and voila! A new urban art form is born that can sense its audience, react and vary the imagery according to it.

Spray-on ICs - why not? Here are some links to some other, perhaps less-anticipated products offered in such a form:

http://gizmodo.com/gadgets/technology/spray-on-a-computer-133076.php

http://nexus404.com/Blog/2006/12/01/spray-condom/

http://www.cpr-savers.com/Industrials/bandas2/bandage%20spray.html

http://www.thisnext.com/item/21BD8AB8/NYC-Organic-Spray-On-Tan

http://www.uniquepaving.com.au/spray-on-paving.htm

Last week, I mentioned that Matsushita might not be getting the respect they deserved with a 45nm process obliterated by Intel’s shadow. I also should acknowledge that I was one of the doubters and expected Intel to not only get to 45nm first but with a considerable lead on second place. Well it turns out that the speculation by Engadget and others coming out of CEATEC was correct. Matsushita (or Panasonic) not only has a real 45nm logic process, but they beat Intel to the market!

Matsushita doesn’t bother with high-k gate dielectrics or metal gate electrodes at 45nm, but they achieve the transistor packing density of the latest technology node. In fact, the Matsushita process beats Intel’s tightest metal pitches. The DVD decoder chip is a complex SoC with over 300 small SRAM arrays scattered around the die. A compact die size of 68 square millimeters certainly would not be possible without a small bit cell design, and Matsushita’s SRAM cell size matches up with Intel. With slightly tighter than 140nm pitch at metals one through four, Matsushita actually has a slight edge over Intel’s 150nm observed pitch.

The UniPhier SoC is truly built to reduce silicon die area and cost. Believe it or not, Panasonic uses it in a video player with a VHS tape bay. That’s something old along with the new in the DMR-XW200V Blu-Ray player. There could be something borrowed as well, but we are still analyzing the device, and I’m not a lawyer.

Finally, let me extend a sincere apology to Matsushita for underestimating their prowess in process technology as well as a hearty congratulations for being the first manufacturer of 45nm logic technology.

Yesterday marked the dawn of a new era of scaling for CMOS devices. I hope that statement fits with all the hype around the launch of the 45nm microprocessor from Intel. In fairness, though, switching to metal gates and high-k dielectrics represents an important milestone in semiconductor technology. Gordon Moore’s well-worn comments are appropriate:

“The implementation of high-k and metal materials marks the biggest change in transistor technology since the introduction of polysilicon gate MOS transistors in the late 1960s.”

Intel released TEM images of its 45nm PMOS transistor. The embedded SiGe source / drains are evident, but we’ve all seen those before. For his keynote, Paul Otellini seemed confident that we could not tell what Intel’s secret sauce in the dielectric and workfunction metals was, but they had something to hide on top of the gate stack. We can’t see the CMP surface, but that’s a no-brainer for a replacement gate (aka gate last) technique. I think they want to keep the capping material on top of the gate electrode hidden until they present at IEDM (Paper 10.2). At about 9:30 on the morning of December 11 in Washington, DC, Kaizad Mistry will open the trench coat on the 45nm HKMG process. Considering the secrecy Intel has been able to maintain on this process, I think the trench coat is a fair reference. Intel deserves full marks for keeping its employees and vendors quiet for so long. Steve Jobs is jealous, I’m sure.

Or maybe he’s not. SI will be opening the kimono on the Penryn this Friday to all our clients participating in the analysis. Intel will still generate lots of excitement at IEDM (at least if you aren’t analyzing 45nm or buying one of our reports).

There’s been much hype and there will be much more.  The Penryn MPU hit Time magazine’s list of best inventions of 2007 along with the iPhone cover girl. Intel may covet the iPhone socket and may well win it for next generation devices, but there may could be another connection to Time’s list. NASA’s methane powered rocket might one day look to the Intel marketing machine as a steady source of fuel.

While attending the IBM and associates Common Technology Platform Forum this afternoon, it occured to me that I was bridging the gap between the design community and trying to get it right, and the failure analysis community that steps in too often to mention in polite company. That’s because I am also in San Jose to attend the International Symposium on Testing and Failure Analysis (ISTFA). The gap is more than a conceptual one as well since there are few if any slick executives at ISTFA. In fact, “engineer” is a word that is spoken in a somewhat unflattering fashion by many ISTFA presenters. But I refuse to hide my iron ring. (Big deal, I know since Canadians are in short supply at these events. Maybe at tonight’s Sharks game, it would be recognized but SI still hasn’t heeded requests to include pro-sports packages into corporate travel arrangements.) Since so many failure analysts are engineers, I guess it’s really designers - not engineers at large - that are the brunt of this abuse.

Intel Fellow Dr. Mario Paniccia enlightened the crowd with Silicon Photonics: Opportunity, Challenges & Applications. Dr. Paniccia is director of the photonics technology lab, but he got his start in quality and reliability at Intel. In fact, this appears to be how Intel decided that optical components on silicon made sense. It was the success of optical fault isolation and analysis tools used in silicon FA that got them thinking. If electro-optical interactions in silicon could be exploited for detecting failures, why not find a way to make photonic devices?

Without going into too much detail (I would not do it justice anyway), waveguides can be built very effectively on SOI. The game-changer for photonics is that silicon has patterning and processing tools available that are leagues ahead of the III-V equipment. As Dr. Paniccia said, the silicon photonics world can “draft” two or three generations behind Moore’s Law and still produce components that are beyond the wildest dreams of traditional photonics providers in terms of booth footprint and cost.

The trick to making this work is to get lasers and detectors onto silicon. Since silicon is an indirect bandgap material, emitters and detectors are better left to the compound semiconductors. But that is not a real set-back to the silicon developers because complicated packaging and assembly is still required of non-silicon components. Intel has developed ways to align multiple InP-based lasers onto their silicon waveguides at the wafer level. This work, done in collaboration with the University of Santa Barbara, has developed 30+ 40Gb/s parallel tranceivers. Get some more details from the Intel blog.

At this time, I would like to pass along my condolences to the III-V photonics community. With the Intel powerhouse on the verge of making your optical components as dirt cheap and tiny as today’s DRAM and flash, I believe your days are numbered.