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	<title>SemiSerious &#187; Process</title>
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	<link>http://www.semiconductorblog.com</link>
	<description>Revealing commentary and news about the semiconductor industry.</description>
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		<title>The phases, they are a-changin&#8217;</title>
		<link>http://www.semiconductorblog.com/2010/05/14/the-phases-they-are-a-changin/</link>
		<comments>http://www.semiconductorblog.com/2010/05/14/the-phases-they-are-a-changin/#comments</comments>
		<pubDate>Fri, 14 May 2010 18:01:18 +0000</pubDate>
		<dc:creator>Andrew Woodard</dc:creator>
				<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Memory]]></category>
		<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/?p=508</guid>
		<description><![CDATA[According to Numonyx (recently acquired by Micron) and Samsung, the times may indeed be a-changin’ when it comes to memory system design.  Just like theoretical physicists have been in search of a unified field theory to explain everything from gravity to electromagnetics to nuclear forces, memory designers have been in search of the ultimate memory that can do it all – fast access, non-volatility, high density, low cost, and low power consumption.]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2010/05/14/the-phases-they-are-a-changin/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>IMFT 25nm NAND flash:  Seeing Double (patterning)</title>
		<link>http://www.semiconductorblog.com/2010/03/08/imft-25nm-nand-flash-seeing-double-patterning/</link>
		<comments>http://www.semiconductorblog.com/2010/03/08/imft-25nm-nand-flash-seeing-double-patterning/#comments</comments>
		<pubDate>Mon, 08 Mar 2010 13:00:08 +0000</pubDate>
		<dc:creator>Andrew Woodard</dc:creator>
				<category><![CDATA[Memory]]></category>
		<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/?p=491</guid>
		<description><![CDATA[It seems that a 25nm half pitch NAND flash process would have to use double patterning to defeat the limits imposed by the Rayleigh criterion.  In the self-aligned STI is proof that will have you seeing double.... patterning that is.]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2010/03/08/imft-25nm-nand-flash-seeing-double-patterning/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Micron/Nanya debut 42nm SDRAM</title>
		<link>http://www.semiconductorblog.com/2010/02/08/micronnanya-debut-42nm-sdram/</link>
		<comments>http://www.semiconductorblog.com/2010/02/08/micronnanya-debut-42nm-sdram/#comments</comments>
		<pubDate>Mon, 08 Feb 2010 15:57:02 +0000</pubDate>
		<dc:creator>Andrew Woodard</dc:creator>
				<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Memory]]></category>
		<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/?p=472</guid>
		<description><![CDATA[Seems like it was just last week (actually, 7 days ago to the hour) that Micron was unveiling its newest, smallest NAND flash process to date. This week, they’re at it again:  Jointly developed with Nanya, the 42nm 2Gb DDR3 SDRAM, with a 49.2mm2 footprint, packs 41.6 Mb into each square millimeter. Having just had [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2010/02/08/micronnanya-debut-42nm-sdram/feed/</wfw:commentRss>
		<slash:comments>1</slash:comments>
		</item>
		<item>
		<title>NAND flash frontier reaches 25nm thanks to Intel, Micron</title>
		<link>http://www.semiconductorblog.com/2010/02/01/nand-flash-frontier-reaches-25nm-thanks-to-intel-micron/</link>
		<comments>http://www.semiconductorblog.com/2010/02/01/nand-flash-frontier-reaches-25nm-thanks-to-intel-micron/#comments</comments>
		<pubDate>Mon, 01 Feb 2010 16:00:52 +0000</pubDate>
		<dc:creator>Andrew Woodard</dc:creator>
				<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Memory]]></category>
		<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/?p=467</guid>
		<description><![CDATA[IMFT, the flash memory joint venture between Intel and Micron, announce today that they are sampling 25nm 2-bit-per-cell NAND flash devices in densities up to 64Gb (167mm2).  In doing so they become the current “kings of the mountain” with bragging rights on bits per mm2 (392Mb/mm2) and finest line pitch in a launched product.  They [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2010/02/01/nand-flash-frontier-reaches-25nm-thanks-to-intel-micron/feed/</wfw:commentRss>
		<slash:comments>1</slash:comments>
		</item>
		<item>
		<title>Intel&#8217;s tweak to plug the leak</title>
		<link>http://www.semiconductorblog.com/2010/01/15/intels-tweak-to-plug-the-leak/</link>
		<comments>http://www.semiconductorblog.com/2010/01/15/intels-tweak-to-plug-the-leak/#comments</comments>
		<pubDate>Fri, 15 Jan 2010 13:00:34 +0000</pubDate>
		<dc:creator>Andrew Woodard</dc:creator>
				<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Process]]></category>
		<category><![CDATA[32nm]]></category>
		<category><![CDATA[45nm]]></category>
		<category><![CDATA[High-K]]></category>
		<category><![CDATA[HKMG]]></category>
		<category><![CDATA[intel]]></category>
		<category><![CDATA[leakage]]></category>
		<category><![CDATA[Penryn]]></category>
		<category><![CDATA[power dissipation]]></category>
		<category><![CDATA[Westmere]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/?p=442</guid>
		<description><![CDATA[Intel's second generation high-K gate dielectric further reduces gate-substrate tunnel current.]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2010/01/15/intels-tweak-to-plug-the-leak/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>MISFETs at VLSLI 2009</title>
		<link>http://www.semiconductorblog.com/2009/06/14/misfets-at-vlsli-2009/</link>
		<comments>http://www.semiconductorblog.com/2009/06/14/misfets-at-vlsli-2009/#comments</comments>
		<pubDate>Mon, 15 Jun 2009 03:22:20 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Event Coverage]]></category>
		<category><![CDATA[Game consoles]]></category>
		<category><![CDATA[ITRS]]></category>
		<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Memory]]></category>
		<category><![CDATA[Process]]></category>
		<category><![CDATA[16nm]]></category>
		<category><![CDATA[Ge MISFET]]></category>
		<category><![CDATA[High-K]]></category>
		<category><![CDATA[HKMG]]></category>
		<category><![CDATA[intel]]></category>
		<category><![CDATA[Toshiba]]></category>
		<category><![CDATA[VLSI Symposium]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/?p=331</guid>
		<description><![CDATA[

I mentioned elsewhere that Intel&#8217;s approach of removing the oxide interlayer prior to high-K dielectric deposition was a significant advance on the road to scaling HKMG processes for the 16nm node.  This  joint effort with Sematech and UT Dallas will be presented at VLSI Technology Symposium 2009. Intel&#8217;s oxide-less gate stack technique might be signaling [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2009/06/14/misfets-at-vlsli-2009/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Weak Node</title>
		<link>http://www.semiconductorblog.com/2009/04/28/weak-node/</link>
		<comments>http://www.semiconductorblog.com/2009/04/28/weak-node/#comments</comments>
		<pubDate>Tue, 28 Apr 2009 20:40:04 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[ITRS]]></category>
		<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Process]]></category>
		<category><![CDATA[28nm]]></category>
		<category><![CDATA[32nm]]></category>
		<category><![CDATA[40nm]]></category>
		<category><![CDATA[45nm]]></category>
		<category><![CDATA[ibm]]></category>
		<category><![CDATA[intel]]></category>
		<category><![CDATA[tsmc]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/?p=282</guid>
		<description><![CDATA[As I mentioned last week, there&#8217;s a lot of discussion about half nodes and &#8220;weak&#8221; nodes for logic technology. There&#8217;s no disputing that the semiconductor business ebbs and flows in predictable cycles, so there are points in time where the business climate may just not support gearing up for high volume production. If a downturn [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2009/04/28/weak-node/feed/</wfw:commentRss>
		<slash:comments>1</slash:comments>
		</item>
		<item>
		<title>TSMC 40nm Technology</title>
		<link>http://www.semiconductorblog.com/2009/04/21/tsmc-40nm-technology/</link>
		<comments>http://www.semiconductorblog.com/2009/04/21/tsmc-40nm-technology/#comments</comments>
		<pubDate>Tue, 21 Apr 2009 19:44:12 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/?p=275</guid>
		<description><![CDATA[TSMC recently launched their 40nm process technology. The first devices to roll out of Hsinchu were Altera&#8217;s Stratix IV FPGA&#8217;s. Semiconductor Insights process analysis team was the first to dig into TSMC&#8217;s newest offering.

TSMC&#8217;s 40nm process is a big milestone. They are the first foundry besides IBM to use embedded SiGe source/drains. The eSiGe provides [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2009/04/21/tsmc-40nm-technology/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Insight Awards Selections</title>
		<link>http://www.semiconductorblog.com/2009/03/04/insight-awards-selections/</link>
		<comments>http://www.semiconductorblog.com/2009/03/04/insight-awards-selections/#comments</comments>
		<pubDate>Wed, 04 Mar 2009 12:48:49 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Events]]></category>
		<category><![CDATA[Memory]]></category>
		<category><![CDATA[Process]]></category>
		<category><![CDATA[Semiconductor Insights]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/?p=243</guid>
		<description><![CDATA[This week marks the beginning of the long and sometimes arduous process of selecting winners in the SI Insight Awards in each of the technology categories. Of course, these are:

Process Technology
Non-volatile Memory
DRAM
Mobile Processor

Of course, it&#8217;s always a treat to talk to the creators of technology about their products. Sometimes, it&#8217;s more like listening to proud [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2009/03/04/insight-awards-selections/feed/</wfw:commentRss>
		<slash:comments>2</slash:comments>
		</item>
		<item>
		<title>OmniBSI</title>
		<link>http://www.semiconductorblog.com/2008/05/29/omnibsi/</link>
		<comments>http://www.semiconductorblog.com/2008/05/29/omnibsi/#comments</comments>
		<pubDate>Thu, 29 May 2008 20:00:18 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2008/05/29/omnibsi/</guid>
		<description><![CDATA[This week presented interesting news as two image sensor technologies I thought might one day displace traditional types appear to have made breakthroughs on the march to commercialization. NHK showcased an active layer over IC &#8211; or AIC -type of sensor while OmniVision announced they would be sampling a backside illuminated - BSI - detector next month. Junko Yoshida&#8217;s detailed article on EETimes put [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2008/05/29/omnibsi/feed/</wfw:commentRss>
		<slash:comments>1</slash:comments>
		</item>
		<item>
		<title>Phony Image Sensors</title>
		<link>http://www.semiconductorblog.com/2008/05/01/phony-image-sensors/</link>
		<comments>http://www.semiconductorblog.com/2008/05/01/phony-image-sensors/#comments</comments>
		<pubDate>Thu, 01 May 2008 19:56:13 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2008/05/01/phony-image-sensors/</guid>
		<description><![CDATA[A couple of my colleagues were surprised to say the least this week when the devices they were working on turned out to be rather elaborate fakes. Or not &#8211; I&#8217;m not exactly sure.
SI was undertaking a reverse engineering project looking at a certain leading CMOS image sensor supplier&#8217;s device who is known to use [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2008/05/01/phony-image-sensors/feed/</wfw:commentRss>
		<slash:comments>1</slash:comments>
		</item>
		<item>
		<title>45nm:  What Intel Didn&#8217;t Tell You</title>
		<link>http://www.semiconductorblog.com/2008/01/23/45nm-what-intel-didnt-tell-you/</link>
		<comments>http://www.semiconductorblog.com/2008/01/23/45nm-what-intel-didnt-tell-you/#comments</comments>
		<pubDate>Wed, 23 Jan 2008 19:28:11 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2008/01/23/45nm-what-intel-didnt-tell-you/</guid>
		<description><![CDATA[This article originally appeared in EETimes Under the Hood. Unfortunately, there was an editing hiccup, so I have decided to post the complete text of the original article here. -Ed 
Two months after Semiconductor Insights provided the first public view of Intel&#8217;s 45nm technology and nearly a month after Intel&#8217;s IEDM presentation, it seems appropriate to revisit [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2008/01/23/45nm-what-intel-didnt-tell-you/feed/</wfw:commentRss>
		<slash:comments>1</slash:comments>
		</item>
		<item>
		<title>ITRS Pre-release</title>
		<link>http://www.semiconductorblog.com/2008/01/22/itrs-pre-release/</link>
		<comments>http://www.semiconductorblog.com/2008/01/22/itrs-pre-release/#comments</comments>
		<pubDate>Tue, 22 Jan 2008 21:17:23 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[ITRS]]></category>
		<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2008/01/22/itrs-pre-release/</guid>
		<description><![CDATA[Today Laura Peters from Semiconductor International (the other SI) hosted a webcast providing an overview of the contents of the upcoming 2007 Edition of the Semiconductor Industry Association&#8217;s (SIA) roadmap for technology &#8211; the ITRS. If there is anyone who really knows what&#8217;s in that upcoming document, it is Intel&#8217;s Alan Allan, and he gave [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2008/01/22/itrs-pre-release/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>45nm Mistry</title>
		<link>http://www.semiconductorblog.com/2007/12/12/45nm-mistry/</link>
		<comments>http://www.semiconductorblog.com/2007/12/12/45nm-mistry/#comments</comments>
		<pubDate>Wed, 12 Dec 2007 20:46:40 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Event Coverage]]></category>
		<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/12/12/45nm-mistry/</guid>
		<description><![CDATA[Okay, so this post is a day after the news, but that&#8217;s still better than posting beforehand to create the appearance of a scoop. Yesterday, Intel&#8217;s much anticipated presentation of their 45nm process was held at IEDM in Washington. Although I suggested last week that Intel would reveal certain details of their process, much of it still remains [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2007/12/12/45nm-mistry/feed/</wfw:commentRss>
		<slash:comments>2</slash:comments>
		</item>
		<item>
		<title>Intel DFV</title>
		<link>http://www.semiconductorblog.com/2007/12/06/intel-dfv/</link>
		<comments>http://www.semiconductorblog.com/2007/12/06/intel-dfv/#comments</comments>
		<pubDate>Thu, 06 Dec 2007 22:46:52 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Event Coverage]]></category>
		<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/12/06/intel-dfv/</guid>
		<description><![CDATA[

 
At the Common Platform Technology Forum last month, the design for manufacturing (DFM) session message was, “not if but when the industry will have to move to structured gate layouts.” Intel already has.
The industry is at a point where design for variability (DFV) is required. The old approach would be to add margin, but design [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2007/12/06/intel-dfv/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Spray-on IC</title>
		<link>http://www.semiconductorblog.com/2007/11/29/spray-on-ic/</link>
		<comments>http://www.semiconductorblog.com/2007/11/29/spray-on-ic/#comments</comments>
		<pubDate>Thu, 29 Nov 2007 17:42:44 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/11/29/spray-on-ic/</guid>
		<description><![CDATA[MIT Technology Review ran a very interesting story about printable electronics this week. Kovio, a company spun out of MIT&#8217;s Media Lab, announced a new process for printing transistors with inkjet printing techniques. According to this report, Kovio may begin production with disposable smart cards for public transit. Performance of Kovio devices will be better [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2007/11/29/spray-on-ic/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>R-E-S-P-E-C-T</title>
		<link>http://www.semiconductorblog.com/2007/11/22/r-e-s-p-e-c-t/</link>
		<comments>http://www.semiconductorblog.com/2007/11/22/r-e-s-p-e-c-t/#comments</comments>
		<pubDate>Thu, 22 Nov 2007 17:00:16 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[ITRS]]></category>
		<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/11/22/r-e-s-p-e-c-t/</guid>
		<description><![CDATA[Last week, I mentioned that Matsushita might not be getting the respect they deserved with a 45nm process obliterated by Intel&#8217;s shadow. I also should acknowledge that I was one of the doubters and expected Intel to not only get to 45nm first but with a considerable lead on second place. Well it turns out that the speculation by [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2007/11/22/r-e-s-p-e-c-t/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Penryn Premiere</title>
		<link>http://www.semiconductorblog.com/2007/11/13/penryn-premiere/</link>
		<comments>http://www.semiconductorblog.com/2007/11/13/penryn-premiere/#comments</comments>
		<pubDate>Tue, 13 Nov 2007 18:54:44 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Events]]></category>
		<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Process]]></category>
		<category><![CDATA[Uncategorized]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/11/13/penryn-premiere/</guid>
		<description><![CDATA[Yesterday marked the dawn of a new era of scaling for CMOS devices. I hope that statement fits with all the hype around the launch of the 45nm microprocessor from Intel. In fairness, though, switching to metal gates and high-k dielectrics represents an important milestone in semiconductor technology. Gordon Moore&#8217;s well-worn comments are appropriate:
&#8220;The implementation [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2007/11/13/penryn-premiere/feed/</wfw:commentRss>
		<slash:comments>3</slash:comments>
		</item>
		<item>
		<title>Design, Build, Fail and Test</title>
		<link>http://www.semiconductorblog.com/2007/11/07/design-build-fail-and-test/</link>
		<comments>http://www.semiconductorblog.com/2007/11/07/design-build-fail-and-test/#comments</comments>
		<pubDate>Wed, 07 Nov 2007 22:03:16 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Event Coverage]]></category>
		<category><![CDATA[Events]]></category>
		<category><![CDATA[ITRS]]></category>
		<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/11/07/design-build-fail-and-test/</guid>
		<description><![CDATA[While attending the IBM and associates Common Technology Platform Forum this afternoon, it occured to me that I was bridging the gap between the design community and trying to get it right, and the failure analysis community that steps in too often to mention in polite company. That&#8217;s because I am also in San Jose [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2007/11/07/design-build-fail-and-test/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>The IFM</title>
		<link>http://www.semiconductorblog.com/2007/11/06/the-ifm/</link>
		<comments>http://www.semiconductorblog.com/2007/11/06/the-ifm/#comments</comments>
		<pubDate>Tue, 06 Nov 2007 21:00:36 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Event Coverage]]></category>
		<category><![CDATA[Events]]></category>
		<category><![CDATA[ITRS]]></category>
		<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/11/06/the-ifm/</guid>
		<description><![CDATA[The new buzz word &#8211; acronym actually &#8211; coming out of today&#8217;s IBM-Chartered-Samsung Common Platform Forum today here in Santa Clara is the term introduced by Qualcomm Senior VP and GM, Behrooz Abdi. His view of the consortium is to create an &#8220;integrated fabless manufacturer&#8221; or IFM akin to the IDM he means to displace. (Qualcomm [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2007/11/06/the-ifm/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>45nm: Who will be first?</title>
		<link>http://www.semiconductorblog.com/2007/10/26/45nm-who-will-be-first/</link>
		<comments>http://www.semiconductorblog.com/2007/10/26/45nm-who-will-be-first/#comments</comments>
		<pubDate>Fri, 26 Oct 2007 15:11:06 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/10/26/45nm-who-will-be-first/</guid>
		<description><![CDATA[Well, I certainly believed it would be Intel before Engagdget started trying to change my mind. That site claimed that Panasonic Blu-ray DVD recorders seen at CEATEC contained the UniPhier (Universal Platform for High-quality Image Enhancing Revolution) chip allegedly built with Matsushita&#8217;s 45nm technology. The DVD units are scheduled to roll November 1. Engagdget previously reported [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2007/10/26/45nm-who-will-be-first/feed/</wfw:commentRss>
		<slash:comments>1</slash:comments>
		</item>
		<item>
		<title>Oddjobs</title>
		<link>http://www.semiconductorblog.com/2007/10/09/oddjobs/</link>
		<comments>http://www.semiconductorblog.com/2007/10/09/oddjobs/#comments</comments>
		<pubDate>Tue, 09 Oct 2007 20:18:54 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Packaging]]></category>
		<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/10/09/oddjobs/</guid>
		<description><![CDATA[Steve Jobs may have a golden touch, but who would have ever connected Apple’s iPhone to the sixties Bond classic, Goldfinger? Well, some folks at Cambridge Silicon Radio (CSR) did. Some CSR chip designers were either great James Bond fans or not quite fans of one particular project. (I trust they weren&#8217;t talking about Steve.) [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2007/10/09/oddjobs/feed/</wfw:commentRss>
		<slash:comments>1</slash:comments>
		</item>
		<item>
		<title>iPhone SiP, PoP, SoC</title>
		<link>http://www.semiconductorblog.com/2007/10/03/iphone-sip-pop-soc/</link>
		<comments>http://www.semiconductorblog.com/2007/10/03/iphone-sip-pop-soc/#comments</comments>
		<pubDate>Wed, 03 Oct 2007 13:48:08 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Packaging]]></category>
		<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/10/03/iphone-sip-pop-soc/</guid>
		<description><![CDATA[Confusion abounds about the manufacturer and type of microprocessor found in Apple&#8217;s iPhone. With over a million units shipped to date and Apple on the verge of launching their revolutionary computing platform into Europe, the timing is right to reveal the &#8220;secret.&#8221; Actually, I am just revisiting Semiconductor Insights&#8217; revelation from July as reported in [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2007/10/03/iphone-sip-pop-soc/feed/</wfw:commentRss>
		<slash:comments>1</slash:comments>
		</item>
		<item>
		<title>Just Do It</title>
		<link>http://www.semiconductorblog.com/2007/09/27/just-do-it/</link>
		<comments>http://www.semiconductorblog.com/2007/09/27/just-do-it/#comments</comments>
		<pubDate>Thu, 27 Sep 2007 18:01:42 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/09/27/just-do-it/</guid>
		<description><![CDATA[Slogans, marketing, and heavy-handed branding dominate our consumer society. Whether we are letting our fingers do the walking, in good hands with All-State, or the best a man can get, it&#8217;s hard to escape the advertisers who maximize every opportunity to shape our thinking. The tech world is no different of course. We have &#8220;Intel [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2007/09/27/just-do-it/feed/</wfw:commentRss>
		<slash:comments>1</slash:comments>
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		<item>
		<title>More Buzz</title>
		<link>http://www.semiconductorblog.com/2007/09/06/more-buzz/</link>
		<comments>http://www.semiconductorblog.com/2007/09/06/more-buzz/#comments</comments>
		<pubDate>Thu, 06 Sep 2007 23:51:09 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Process]]></category>
		<category><![CDATA[Uncategorized]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/09/06/more-buzz/</guid>
		<description><![CDATA[A couple weeks ago I scratched rather shallowly into the topic of turning motion energy into useful electricity (check it out). I was impressed with the development of a technology that could convert power line frequency mechanical vibrations into about 40mW from a device fitting inside a one centimetre cube. This, I argued, would start [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2007/09/06/more-buzz/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Nanotechnology from Gigatools</title>
		<link>http://www.semiconductorblog.com/2007/07/19/nanotechnology-from-gigatools/</link>
		<comments>http://www.semiconductorblog.com/2007/07/19/nanotechnology-from-gigatools/#comments</comments>
		<pubDate>Thu, 19 Jul 2007 14:25:42 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Process]]></category>
		<category><![CDATA[Uncategorized]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/07/19/nanotechnology-from-gigatools/</guid>
		<description><![CDATA[Since I&#8217;m not at Semicon West this week to talk to any of the industry movers and shakers, I will take certain liberties to comment on a recent EDN interview with Applied Materials CEO, Mike Splinter.
Ed Sperling looked to extract some information about AMAT&#8217;s success in the tool business. Splinter pointed to recognizing and concentrating on [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2007/07/19/nanotechnology-from-gigatools/feed/</wfw:commentRss>
		<slash:comments>2</slash:comments>
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		<item>
		<title>iPhone Sends Out S-O-S to the World</title>
		<link>http://www.semiconductorblog.com/2007/07/04/iphone-sends-out-s-o-s-to-the-world/</link>
		<comments>http://www.semiconductorblog.com/2007/07/04/iphone-sends-out-s-o-s-to-the-world/#comments</comments>
		<pubDate>Wed, 04 Jul 2007 21:29:33 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Process]]></category>
		<category><![CDATA[Semiconductor Insights]]></category>
		<category><![CDATA[Uncategorized]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/07/04/iphone-sends-out-s-o-s-to-the-world/</guid>
		<description><![CDATA[If you just crawled out from under a rock or you were too busy filling orders for Saskatchewan sealskin bindings, you may not have heard about Apple&#8217;s iPhone launch last Friday. Fortunately, we did, and our crack marketing team stood in a Boston Apple Store line for 12 hours, raced back to HQ here in Ottawa, and [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2007/07/04/iphone-sends-out-s-o-s-to-the-world/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
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		<item>
		<title>We&#8217;ve Got the Power</title>
		<link>http://www.semiconductorblog.com/2007/06/28/weve-got-the-power/</link>
		<comments>http://www.semiconductorblog.com/2007/06/28/weve-got-the-power/#comments</comments>
		<pubDate>Thu, 28 Jun 2007 20:30:59 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Event Coverage]]></category>
		<category><![CDATA[Events]]></category>
		<category><![CDATA[Process]]></category>
		<category><![CDATA[Uncategorized]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/06/28/weve-got-the-power/</guid>
		<description><![CDATA[
Trying to mute the old joke that compound semiconductors are the technology of the future and always will be, Dr. Vu Ho recently attended the 2007 International Conference on Compound Semiconductor Manufacturing Technology. The III-V compounds and related materials such as GaAs, GaN and InP have for years been a mainstay of advanced platforms in [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2007/06/28/weve-got-the-power/feed/</wfw:commentRss>
		<slash:comments>1</slash:comments>
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		<item>
		<title>2007 IEEE International Interconnect Technology Conference</title>
		<link>http://www.semiconductorblog.com/2007/06/19/2007-ieee-international-interconnect-technology-conference/</link>
		<comments>http://www.semiconductorblog.com/2007/06/19/2007-ieee-international-interconnect-technology-conference/#comments</comments>
		<pubDate>Tue, 19 Jun 2007 18:27:26 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Event Coverage]]></category>
		<category><![CDATA[Events]]></category>
		<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Process]]></category>
		<category><![CDATA[Uncategorized]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/06/19/2007-ieee-international-interconnect-technology-conference/</guid>
		<description><![CDATA[A couple of weeks ago, my good friend and semiconductor analysis colleague, Mark Chambers, attended the IITC in San Francisco. The sessions were held from June 4 to 6 at the Hyatt Regency at San Francisco Airport. Because the dates spanned my wedding anniversary and wife&#8217;s birthday and the conference site was far from downtown, [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2007/06/19/2007-ieee-international-interconnect-technology-conference/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>VLSI &#8211; DRAM Technology</title>
		<link>http://www.semiconductorblog.com/2007/05/09/vlsi-dram-technology/</link>
		<comments>http://www.semiconductorblog.com/2007/05/09/vlsi-dram-technology/#comments</comments>
		<pubDate>Wed, 09 May 2007 20:14:49 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Events]]></category>
		<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Memory]]></category>
		<category><![CDATA[Process]]></category>
		<category><![CDATA[Uncategorized]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/05/09/vlsi-dram-technology/</guid>
		<description><![CDATA[With the VLSI Syymposia just a little over a month away, I will wrap up my picks for papers to watch for by looking at DRAM. For the Technology Symposium, Samsung is over-represented with five out of the seven presentations split between two sessions.
Two of Samsung&#8217;s articles will discuss aspects of their FinFET DRAM cell, [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2007/05/09/vlsi-dram-technology/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
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		<item>
		<title>VLSI 2007 &#8211; Phase Change Memory Technology</title>
		<link>http://www.semiconductorblog.com/2007/04/17/vlsi-2007-phase-change-memory-technology/</link>
		<comments>http://www.semiconductorblog.com/2007/04/17/vlsi-2007-phase-change-memory-technology/#comments</comments>
		<pubDate>Tue, 17 Apr 2007 21:49:25 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Events]]></category>
		<category><![CDATA[Memory]]></category>
		<category><![CDATA[Process]]></category>
		<category><![CDATA[Uncategorized]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/04/17/vlsi-2007-phase-change-memory-technology/</guid>
		<description><![CDATA[This is my second review of papers to be presented at the VLSI Technology Symposium. Today, I will take a look at the most promising papers on phase change memory technology (PCM or PRAM). Today at its spring development forum in Beijing, Intel announced that it will produce a 128M 90nm PRAM later this year. This is bound to create some extra buzz [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2007/04/17/vlsi-2007-phase-change-memory-technology/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
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		<item>
		<title>TSMC 45nm ready in September &#8211; what&#8217;s changed?</title>
		<link>http://www.semiconductorblog.com/2007/04/10/tsmc-45nm-ready-in-september-for-what/</link>
		<comments>http://www.semiconductorblog.com/2007/04/10/tsmc-45nm-ready-in-september-for-what/#comments</comments>
		<pubDate>Tue, 10 Apr 2007 19:35:20 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/04/10/tsmc-45nm-ready-in-september-for-what/</guid>
		<description><![CDATA[TSMC recently announced it would put its 45nm technology into production this coming September. For me, this begs the question, &#8220;What&#8217;s changed?&#8221; After all, TSMC was relatively late to the 65nm party. Consider the following:

65nm was generally a shrink of 90nm
45nm will be &#8220;new&#8221;
TSMC followed most of the major IDMs and rival UMC into 65nm production
The [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2007/04/10/tsmc-45nm-ready-in-september-for-what/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>VLSI 2007</title>
		<link>http://www.semiconductorblog.com/2007/04/02/vlsi-2007/</link>
		<comments>http://www.semiconductorblog.com/2007/04/02/vlsi-2007/#comments</comments>
		<pubDate>Mon, 02 Apr 2007 14:20:59 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Events]]></category>
		<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Process]]></category>
		<category><![CDATA[Uncategorized]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/04/02/vlsi-2007/</guid>
		<description><![CDATA[Once again last week, the organizers of the VLSI Technology and Circuit Symposia organizers supplied me with this year&#8217;s abstracts and conference summary. As always, there are a lot of great papers with all geographic regions well-represented. For today&#8217;s blog, I will start a series of posts about which papers and technologies to watch for [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2007/04/02/vlsi-2007/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
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		<item>
		<title>Fusion Memory</title>
		<link>http://www.semiconductorblog.com/2007/03/20/fusion-memory/</link>
		<comments>http://www.semiconductorblog.com/2007/03/20/fusion-memory/#comments</comments>
		<pubDate>Tue, 20 Mar 2007 20:12:59 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Industry News]]></category>
		<category><![CDATA[Memory]]></category>
		<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/03/20/fusion-memory/</guid>
		<description><![CDATA[In one of three plenary talks given at the 2006 International Electron Devices Meeting (IEDM), Dr. Chang-Gyu Hwang, president and CEO of Samsung Electronics&#8217; Semiconductor Business, suggested that we are about to experience the largest semiconductor industry transition ever. Chip Shots and Physorg have more detailed accounts of this talk.
An entertaining Dr. Hwang predicted, “The approaching [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2007/03/20/fusion-memory/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
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		<item>
		<title>The Priory of 65nm SiON</title>
		<link>http://www.semiconductorblog.com/2007/03/05/the-priory-of-65nm-sion/</link>
		<comments>http://www.semiconductorblog.com/2007/03/05/the-priory-of-65nm-sion/#comments</comments>
		<pubDate>Mon, 05 Mar 2007 21:57:19 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/03/05/the-priory-of-65nm-sion/</guid>
		<description><![CDATA[
Perhaps the DaVinci Code and the legend of the Priory of Sion is no longer topical, but Sion’s namesake compound – SiON or silicon oxynitride – is extremely relevant in the semiconductor industry. Unlike Sion though, SiON at 65nm is no hoax – pushing exotic high-K materials out to 45nm for high performance logic processes [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2007/03/05/the-priory-of-65nm-sion/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>2D or 3D? That is the question.</title>
		<link>http://www.semiconductorblog.com/2007/02/12/2d-or-3d-that-is-the-question/</link>
		<comments>http://www.semiconductorblog.com/2007/02/12/2d-or-3d-that-is-the-question/#comments</comments>
		<pubDate>Mon, 12 Feb 2007 20:00:18 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/02/12/2d-or-3d-that-is-the-question/</guid>
		<description><![CDATA[45 years ago, planarization of the integrated circuit was a revolution that spawned Moore’s Law. Robert Noyce’s work took the idea of the IC in a direction that arguably shaped our information age.
For the last several years, we braced for the end of Moore’s Law because planar technology would not continue to scale fast enough. [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2007/02/12/2d-or-3d-that-is-the-question/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>More to RCAT than Samsung</title>
		<link>http://www.semiconductorblog.com/2006/12/20/more-to-rcat-than-samsung/</link>
		<comments>http://www.semiconductorblog.com/2006/12/20/more-to-rcat-than-samsung/#comments</comments>
		<pubDate>Thu, 21 Dec 2006 00:32:43 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/?p=5</guid>
		<description><![CDATA[In the constant quest to increase the density of memory bits in each square millimeter of silicon, DRAM makers have looked up and down. First, there were storage capacitors stacked above the active devices. Then IBM developed trench technology (now widely exploited by Qimonda) to bury the capacitor deep into the substrate.
More recently, Samsung introduced [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2006/12/20/more-to-rcat-than-samsung/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Intel 65nm NOR StrataFlash</title>
		<link>http://www.semiconductorblog.com/2006/12/12/intel-65nm-nor-strataflash/</link>
		<comments>http://www.semiconductorblog.com/2006/12/12/intel-65nm-nor-strataflash/#comments</comments>
		<pubDate>Tue, 12 Dec 2006 17:35:30 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Memory]]></category>
		<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/?p=7</guid>
		<description><![CDATA[
Macronix recently announced that phase change memory (PCM) developed jointly with IBM and Qimonda had proven its viability below 20nm. The same DigiTimes article pointed out that this PCM technology proved it could overcome the ?physical barriers? currently inhibiting production of 65nm NOR flash.
These comments are puzzling considering SI has already completed a comprehensive analysis [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2006/12/12/intel-65nm-nor-strataflash/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
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		<title>TI Chip is 65nm Star</title>
		<link>http://www.semiconductorblog.com/2006/11/23/ti-chip-is-65nm-star/</link>
		<comments>http://www.semiconductorblog.com/2006/11/23/ti-chip-is-65nm-star/#comments</comments>
		<pubDate>Thu, 23 Nov 2006 17:11:05 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/?p=9</guid>
		<description><![CDATA[To answer the question posed by Ed Keyes in EETimes, 65nm: Where are the chips?? we can now say, &#8220;TI&#8221;.
Intel was first to 65nm nearly one year ago with their MPU. Then there was UMC getting a Xilinx FPGA into production and AMD with their Opteron G processor. Now comes TI with the first 65nm [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2006/11/23/ti-chip-is-65nm-star/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
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		<item>
		<title>Intel&#8217;s recipe for FUSI</title>
		<link>http://www.semiconductorblog.com/2006/11/09/intels-recipe-for-fusi/</link>
		<comments>http://www.semiconductorblog.com/2006/11/09/intels-recipe-for-fusi/#comments</comments>
		<pubDate>Thu, 09 Nov 2006 19:31:12 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2006/11/09/intels-recipe-for-fusi/</guid>
		<description><![CDATA[Intel was not only the first manufacturer to produce a 65nm advanced logic process, they are also onto their third revision of the generation. Among the tweaks in the Xeon is an increase in germanium concentration. The most striking, though, is that Xeon appears to be the first ever device to use FUSI - or FUlly [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2006/11/09/intels-recipe-for-fusi/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Leaders of the world unite!</title>
		<link>http://www.semiconductorblog.com/2006/10/11/leaders-of-the-world-unite/</link>
		<comments>http://www.semiconductorblog.com/2006/10/11/leaders-of-the-world-unite/#comments</comments>
		<pubDate>Wed, 11 Oct 2006 20:34:12 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2006/10/11/leaders-of-the-world-unite/</guid>
		<description><![CDATA[Two semiconductor manufacturers &#8211; Intel and Micron &#8211; teamed up to create IM Flash Technologies (IMFT). This partnership is the first to reach the 50nm half-pitch generation.

This marks the first time in recent times Samsung has been surpassed in memory process technology. About 12 months ago, flash solidified its position as the new lithography driver [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2006/10/11/leaders-of-the-world-unite/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Organic Produce and DFM</title>
		<link>http://www.semiconductorblog.com/2006/09/26/organic-produce-and-dfm/</link>
		<comments>http://www.semiconductorblog.com/2006/09/26/organic-produce-and-dfm/#comments</comments>
		<pubDate>Tue, 26 Sep 2006 22:06:37 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2006/09/26/organic-produce-and-dfm/</guid>
		<description><![CDATA[


Above: Dummy features?identified on TI OMAP 2420 Applications Processor (Source: Semiconductor Insights)   
More Information
Download a complimentary Insight Report about Texas Instruments OMAP2420 Applications Processor (requires registration)


Aren&#8217;t fruits and vegetables by definition organic? DFM - or design for manufacturability - is a common buzzword these days. Am I alone on this one too, or were we not always designing [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2006/09/26/organic-produce-and-dfm/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>SanDisk tinkers with Matrix 3D Memory</title>
		<link>http://www.semiconductorblog.com/2006/02/13/sandisk-tinkers-with-matrix-3d-memory/</link>
		<comments>http://www.semiconductorblog.com/2006/02/13/sandisk-tinkers-with-matrix-3d-memory/#comments</comments>
		<pubDate>Mon, 13 Feb 2006 15:12:47 +0000</pubDate>
		<dc:creator>Don Scansen</dc:creator>
				<category><![CDATA[Process]]></category>

		<guid isPermaLink="false">http://www.semiconductorblog.com/2007/02/13/sandisk-tinkers-with-matrix-3d-memory/</guid>
		<description><![CDATA[Several weeks ago, I discussed an Ottawa firm’s entry into the one-time programmable (OTP) memory space. My focus in that discussion was the Matrix 3D memory which was also OTP and a rather ingenious way of packing very high numbers of bits onto chips made with older process technology – very old in comparison with [...]]]></description>
		<wfw:commentRss>http://www.semiconductorblog.com/2006/02/13/sandisk-tinkers-with-matrix-3d-memory/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
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