NAND flash frontier reaches 25nm thanks to Intel, Micron
IMFT, the flash memory joint venture between Intel and Micron, announce today that they are sampling 25nm 2-bit-per-cell NAND flash devices in densities up to 64Gb (167mm2). In doing so they become the current “kings of the mountain” with bragging rights on bits per mm2 (392Mb/mm2) and finest line pitch in a launched product. They like to add that it’s not only the smallest NAND pitch, but the smallest pitch in commercial silicon anywhere. That’s not too surprising given that NAND in general is ahead of DRAM, NOR, and logic in terms of raw pitch due to its lithography-friendly long, straight-line layouts. Still, the achievement of a 25nm node leapfrogs IMFT ahead of Toshiba at 32nm and Samsung at 30nm, and even beats out existing 3-bit-per-cell NAND offerings for bit density. In fact, Micron was planning to release a 34nm 3-bit-per-cell NAND device, but the 25nm 2-bit-per-cell technology matched its density with greater performance and reliability, rendering it obsolete before it ever left the front door.
Micron director of strategic NAND marketing and blogger extraordinaire Kevin Kilbuck has told UBM TechInsights that the devices, slated for volume production in Q2 2010, have achieved these unprecedented dimensions with “no major expenditures” on lithography tooling, using “whatever we used on 34nm.” For point of reference, Intel used dry 193nm double patterning for logic critical levels at 45nm and finally bit the bullet and went immersion at 32nm. If IMFT is getting 25nm out of the same equipment set they used at 34nm (a quasi-Mooreian scaling factor of 0.74), then the “major expenditures” (i.e. immersion litho) must have already come at 34nm, which had been postulated at the release of the IMFT 34nm NAND device.
What about die stacking? My guess is that they will offer up to an 8-die stack using wire bonding. Micron is developing a new packaging offering under the name Osmium which includes through-silicon via (“through-wafer interconnect” in their parlance), but wire bonding, as we’ve seen, has legs. It keeps showing up in places where you wouldn’t expect, even in high-I/O devices such as the Freescale QorIQ P2020 comms processor.
Details about the interpoly dielectric and other materials are being kept close to Intel and Micron’s respective chests. Early peeks at TEM cross-sections suggest they’re riding ONO-based stacks one more generation rather than going to a high-K IPD such as aluminum silicon oxide. There are no changes in interconnect or gate materials either. While confirming the obvious, that this is a floating gate memory, Kilbuck would not estimate how many more nodes floating gate will be good for. A move to charge trapping MONOS memory would not be without peril; the IP landscape changes completely. With many fundamental patents still enforceable, licensing costs present a barrier to entry.
Essentially, this is a die shrink enabling Intel and Micron to supply more NAND capacity at a time when demand is showing signs of life for once. More importantly though, it continues the breakneck pace of process technology evolution that has allowed IMFT to catch up with and surpass its competitors. Watch out, Samsung and Toshiba; this is a three-horse race now.