IMFT 25nm NAND flash: Seeing Double (patterning)
Everybody (at least in the circles I run in) is talking about the Micron 25nm manufacturing process that is enabling IMFT to bring the current lowest cost per bit NAND flash memory to market. Speculations abound about which optical lithography enhancements have been used to translate the natural air wavelength of 193nm ArF excimer laser into the 50nm pitches necessary to produce 25nm NAND flash cells.
To provide a bit of background, the Rayleigh criterion describes the ultimate resolution of a lithography system:
R = k1λ / NA
Where R is the feature size (in half pitch), λ is the exposure wavelength, and NA is the numerical aperture of the objective lens system (for those who care, it’s the sine of the objective lens’s acceptance angle times the refractive index of the surrounding medium). k1, the process factor, is an empirically determined (that’s a nice way of saying fudge factor) factor that grades the performance of the minimum printed feature a process is ultimately able to achieve. Techniques such as optical proximity correction, phase shift masking, and off-axis illumination can all help decrease k1. Note that immersion lithography is not considered a k1 reduction technique, but an NA increasing technique. The higher refractive index of water relative to air lowers the angles at which the diffraction orders propagate, allowing extra diffraction orders to be used which would not exist in a dry system. The practical limit for k1 today is considered to be about 0.25, and immersion lithography systems have achieved a maximum NA of 1.35, so it is possible to print in a single exposure a half pitch of 35 nm using such an ideal system. Well, we’re at 25nm now, which must be why Dr. M. David Levenson, formerly of IBM and inventor of the alternating phase shift mask, stated in an interview that Intel and Micron are using sidewall double patterning, and why we believe they were already using it at 34nm, which would have been past the limit for single exposure patterns.
What features on the 25nm NAND flash actually need to be 25nm? The flash cell is a 4F2 which means it is a minimum line and space (2F, with F=25nm) in both the wordline and bitline direction. The wordlines and bitlines need to be 25nm half pitch of course, but the shallow trench isolation needs to be as well, since there must be an STI between every column of cells. As it happens, Micron uses a self-aligned STI process in which the floating gate’s channel width mask pattern serves additionally as an STI pattern. With the same hardmask defining floating gate and STI, there is no misalignment between cell and STI, maximizing coupling capacitance across the tunnel oxide. This technique has been in use for 10 years, since Toshiba’s TC58256DC 256Mb NAND flash, fabricated on the 0.16 micron process. But as I was saying, the mask used to define the STI is sidewall double patterned. Let me define this process for the uninitiated:
- Print a sacrificial feature of size F and pitch 4F
- Strip resist and deposit/etch spacers of thickness F. They should have F space between them.
- Strip out sacrificial feature and etch floating gate/STI using spacer as a hardmask
The STI etch itself is quite challenging; aspect ratios exceed 6:1 in a trench width of ~30nm. At this feature size, etch species and etch product mass transport in and out of the trench, and hence etch rate, depends highly on the width of the trench. This is known as microloading. Controlling trench depth depends on controlling the CD of the mask. Let’s consider what happens when there is a CD error in the double patterned mask. If the sacrificial feature width is F+d, a spacer deposition of F will result in spacers having an alternating spacing of F+ d, F- d. Any linewidth errors manifest themselves as an apparent misalignment of twice the magnitude. Even if the linewidth error is less than your available measurement precision, the differing opening sizes will have a noticeable effect on trench etching.
The small spaces will give rise to shallower trenches than the deep ones. So there it is – the red herring for sidewall double patterned STI is a sawtooth pattern in trench depth. Get used to seeing this in NAND flash memories from now on:
SEM cross section of IMFT 25nm NAND flash in wordline direction
It’s Moore’s Law advancing… on the double.