Micron/Nanya 42nm predictions revisited
On February 8 I tantalized my audience (all two of you) with some guesses as to what UBM TechInsights would find inside the Micron/Nanya 42nm DDR3 SDRAM. With the Detailed Structural Analysis almost ready for publication, I thought I’d go back and check my guesses, while also tipping my lucky readers with a few interesting facts.
Prediction 1: Greater than 7 F2 Cell Size owing to more relaxed bitline pitch relative to wordline pitch.
Correct. With the cell size measuring in officially at 129nm (1.5X wordline pitch) by 99nm (bitline pitch) and using a nominal F of 42nm (the node) we obtain a cell size of 7.24F2 and a BL pitch to WL pitch ratio of 1.15 as opposed to 1.12 with the 50nm DDR2 part. 6F2 design continues to slip in area savings versus 8F2.
Prediction 2: Continued use of wavy bitlines
Correct. I suppose this was a bit of a gimme but if this design is threatening the scaling of the cell, it could certainly change at some point.
Prediction 3: Central layer of high-bandgap material in capacitor dielectric takes up less proportion of stack.
Undecided. All I should say about this one is that the stack is indeed different. They won’t let me see the EDS results because word is I have a big mouth 
Prediction 4: Deeper, non-spherical RCAT.
Not exactly. While I got the non-spherical part right, it seems like the RCAT recess depth is no deeper in 42nm than in 50nm. This must mean that they have a good handle on cell charge retention or that deepening the RCAT presented significant challenges.
Prediction 5: Capacitor aspect ratio over 10 to 1.
Depends on where you measure. If you measure the width as the width of the opening that the lower electrode is deposited into, you get about 10. If you take the width from cap dielectric to cap dielectric, a measure of how hard it is to fill the upper electrode, you get about 11.
Prediction 6: Copper bond wire.
Unknown. Well, as this is a never-bonded engineering sample and parts aren’t available on the open market yet, this can’t be answered. However, I don’t give it a good chance since cross-sections revealed an aluminum top metal rather than a copper/nickel pad.
So, it’s a mixed bag. Some unexpected changes as well as changes where I expected none. You can’t second guess the designer or the process engineer because these chips are the final result of many lot splits and development experiments. However, that’s part of the fun of being an analyst – putting your knowledge out there to predict what future technology will look like.
Come back next week for a second look at the Micron/Intel 25nm NAND flash!