MISFETs at VLSLI 2009
Toshiba's LaAlO3/SrGeX/Ge p-MISFET Gate Stack
I mentioned elsewhere that Intel’s approach of removing the oxide interlayer prior to high-K dielectric deposition was a significant advance on the road to scaling HKMG processes for the 16nm node. This joint effort with Sematech and UT Dallas will be presented at VLSI Technology Symposium 2009. Intel’s oxide-less gate stack technique might be signaling the direction they will be taking for future high-K processing which has a big impact on the rest of the logic manufacturers.
Although I overlooked the non-silicon channel transistor presentations at VLSI 2009, they are certainly a serious contender for future generations like 16nm. Intel themselves spend a great deal of effort seeking a silicon channel replacement. Many of my trusted colleagues believe that a new material will displace silicon for the transistor channel thereby extending the scalability of planar complimentary logic and avoiding the use of multiple gated, vertical channel transistors such as the FinFET. Of course, it’s a dangerous game to point to one Intel paper about technology that’s three nodes down Sheriff Moore’s road when Intel always explores as many technology options as possible before deciding on a direction for future production.
Intel has been busy pursuing possible replacements for silicon as the channel material for transistors., but they certainly aren’t the only ones as Toshiba’s presentation Monday afternoon in Kyoto proves.
In Session 4B devoted to the germanium MOSFET, Toshiba will present “New Approach to Form EOT-Scalable Gate Stack with Strontium Germanide Interlayer for High-k/Ge MISFETs.” The Toshiba paper claims the highest ever hole mobility in a p-channel FET with a peak value quoted of 481cm2/Vs. With only the abstract and the TEM image provided in the Toshiba release, it’s difficult to say how close they are to providing a viable solution for the equivalent oxide thickness (EOT) target of 0.5nm for the 16nm logic generation. The press release reports the cost of the strontium germanide interlayer is to increase the EOT by “only 0.2nm at the most.” It appears that the gate stack reported by Toshiba achieves a total EOT of “as thin as around 1nm.”
Toshiba has clearly done some great work in this area. They have also clearly demonstrated the LaAlO3/SrGeX/Ge p-MISFET as a technology option. But there are many hurdles standing between this work and getting this gate stack ready for the 16nm node. There appears to be less standing in the way of the Intel zero SiOx interface stack which claims an EOT of 0.59nm. That Intel-Sematech-UT Dallas paper will be presented in the Advanced Gate Stacks Session (3A) just a couple of hours before Toshiba.
One thing I really like about this paper is its return to the term MISFET which was sadly replaced long ago by the now familiar MOSFET. For the PR professional, it’s all too close to misfit, of course, but in this new age of non-oxide gate dielectrics and even non-silicon channel materials, a more generic term is needed. Oddly, even the session title for Toshiba’s paper is “Ge MOSFET,” but as their abstract says, the strontium-germanide interlayer avoids the low-K oxides of germanium for the gate dielectric in their germanium channel devices. Still, I hope that even if an oxide ends up in the mix for whatever direction the industry widely adopts, we can keep MISFET because geeks – especially semicon geeks – like to think of themselves at least a little bit like misfits.
Tags: 16nm, Ge MISFET, High-K, HKMG, intel, Toshiba, VLSI Symposium
Posted in Event Coverage, Game consoles, ITRS, Industry News, Memory, Process | No Comments »