Intel’s tweak to plug the leak

While no other semiconductor manufacturer even has a metal gate transistor on the shelf for sale yet, Intel is already on its second generation of the high-K metal gate transistor with the introduction of the Westmere 32nm process.  Easily observable differences between this and the earlier 45nm process include the about 25% reduction in HfO2 thickness and also the order of deposition of the high-K HfO2 dielectric.  Instead of being deposited underneath the dummy poly gate, it is now deposited after dummy poly gate removal.  Thus, it is no longer subjected to the thermal steps of selective epitaxy, implant anneals, or silicidation.

Our Process Comparison of Intel  45nm and 32nm technology reveals another much less apparent difference – the 45nm high-K dielectric was a mixed metal oxide, the majority being hafnium.  This has given way to a substantially pure hafnium dioxide.  Since the mixed metal dielectric had a higher dielectric constant and was more resistant to crystallization, why did they change it?

The answer may lie in gate leakage.  Recall that transistor leakage has two components – subthreshold leakage (source-drain current when transistor is supposed to be “off”) and gate leakage (current passing through the gate dielectric for various reasons, mostly tunneling).  Subthreshold leakage is minimized by having a high capacitance between the gate and the channel, which can be done by increasing the K of the gate dielectric or making it thinner.  However, since thinning the gate dielectric increases gate tunneling current exponentially, process designers must choose a dielectric thickness that strikes a balance between subthreshold leakage and gate leakage.

In migrating from 45nm to 32nm, the EOT (equivalent oxide thickness) had to be scaled down to avoid short channel  effects.  My guess is that Intel ran into gate leakage problems due to a property of the mixed-metal oxide they used at 45nm:  its morphology tends to be rougher than pure HfO2, introducing thin spots which serve as tunneling current centers.  Switching to pure hafnium dioxide alleviated the issue of morphology-related tunneling current, but also introduced two potential problems: lower thermal stability (including lower crystallization temperature) and increased subthreshold swing (number of millivolts required on the gate to cut drain current by one order of magnitude).  We can see now that the lower thermal stability problem forced Intel to defer the high-K deposition until after all the spike anneals and silicidation were complete.

To see how they did on the subthreshold swing and leakage fronts, we turn to the multi-temperature transistor characteristics.  Our analysis shows that the subthreshold swing figures are equal or marginally larger at 32nm than at 45nm.  It also shows that despite the use of a thinner film at the same power supply voltage, gate leakage (normalized to gate width) is down in 32nm versus 45nm.  This confirms the motivation for the change.  Gate leakage is still public enemy #1 for microprocessor power dissipation, and Intel went to significant trouble, reworking the order of their front-end process, to ensure that the ghosts of Prescott space heaters past never come back to haunt them.

Tags: 32nm, 45nm, High-K, HKMG, intel, leakage, Penryn, power dissipation, Westmere
Posted in Industry News, Process | No Comments »