SemiSerious

Brief note from the editor:

People often compliment me on my workload sharing techniques. For those who know me well, it will therefore come as no surprise that today’s article is written by a guest blogger.

Mike Cowan is a 45-year semiconductor industry veteran who worked for 36 years at IBM’s Microelectronics Division in East Fishkill, N.Y. Mike has developed the Cowan LRA Model for forecasting global semiconductor sales.

Mike Cowan’s key indicator of the health of the semiconductor industry is his “Momentum Indicator” or MI. The good news is that the MI has shown a dramatic improvement since its low point last December when actual sales data were almost 35% below the amount forecast in the previous month.

The rest I will leave to Mike’s explanation. He has an excellent set of slides the explain the model as well as providing a lot of useful current data and analysis about the semiconductor market that he will make available if you would like to contact him. His email is

mikedcowan(at)verizon.net.

Just mention that you read about it on SemiSerious, and he will get it to you right away.

- Don

The Cowan LRA Model For Forecasting Global S/C Sales – Overview Of Model And Latest Forecast Results

Model Overview

A semiconductor sales forecasting model has been developed to facilitate the determination of future global sales of the semiconductor industry. The Cowan LRA (Linear Regression Analysis) Model, which forecasts global semiconductor sales, is a mathematically based model that features statistical analysis of the past 25 years of historical, monthly global semiconductor sales numbers that are collected and published by the World Semiconductor Trade Statistics (WSTS) organization. It is a dynamic, mathematically pure view of near-term worldwide semiconductor sales looking forward over the next five quarters. The model is devoid of economic assumptions or emotional biases. It exploits linear regression analysis operating on the appropriately transformed actual monthly semiconductor sales numbers, thereby rendering the global semiconductor sales data highly linear and, therefore, very amenable to linear regression statistical analysis techniques. The numerical transformation of the past 25 years of monthly actual sales numbers — from 1984 through 2008 — that is invoked is not a complicated mathematical expression but very straight forward and makes sense physically, yielding extremely high linear regression correlation coefficients of 0.97 and greater. In exercising the forecasting model each month, a total of five distinct sets of linear regression parameters (of the format y = mx + b) are employed to calculate the resulting global semiconductor sales forecast estimates for each of the next five quarters associated with the model’s forecast horizon.

Cowan LRA Momentum Indicator

It is emphasized that each month’s actual global sales number released by WSTS is a lagging indicator because it is published a full month “after the fact.” The Cowan LRA Model, however, turns this lagging monthly sales result into a leading indicator by virtue of its near-term forecasting capability looking out over the next five quarters. This is the “beauty” of the model and, therefore, makes it dynamic in the sense that it can be run each month using the most recent actual global S/C sales number. Thus it can rigorously track the near-term sales forecast outlook of the global semiconductor industry on a real-time basis. Consequently, the model’s monthly sales forecast does not sit still but evolves each month because conditions change rapidly and unexpectedly in the semiconductor industry, and market forecasts are hard pressed to keep up with these changes. How can industry management be sure that a forecast issued two, three or more months ago is still relevant to what’s happening in today’s market?

Latest Sales Forecast Results

The latest global S/C sales forecast estimates, as derived via exercising the Cowan LRA Model, are based upon the recently-released (on Thursday, 6-04-09) April 2009 actual global S/C sales by the WSTS (note – includes, by the way, very minor upward revisions – i.e., increase in sales – for each of the previous three months of the year, namely, Jan., Feb., and Mar.).

The year 2009 sales forecast estimate kicked up strongly (by $8.52 billion) to $192.50 billion from last month’s sales forecast estimate of $183.99 billion with a corresponding improvement (increase) in the 2009 yr-o-yr sales growth forecast to minus 22.6 percent (from last month’s sales growth forecast estimate of minus 26.0 percent). It should be pointed out that this latest updated sales growth forecast estimate (minus 22.6 percent) is in good agreement with the latest forecast revisions just released by Gartner (minus 22.4 percent), the WSTS (minus 21.6 percent), and the SIA (minus 21.3 percent).

It should be highlighted that this month’s momentum indicator improved (increased) significantly to plus 19.6 percent. This is relatively good news when compared to the actual monthly momentum indicators from Oct08 through Jan09, that is -12%, -26%, -35%, and -31%, respectively. Historical tracking of this particular indicator over the past seven years reveals that the historical long-term trend of this indicator on a monthly basis correlates quite well with the significant collapse in industry sales during the time period just mentioned. Additionally the monthly trend shows a corresponding reversal to be in the making based upon this month’s strongly positive momentum indicator (a record high positive percent since the author has been running the model and tracking this particular indicator).

With this month’s momentum indicator, MI, moving into very high, positive territory bodes well relative to a possible relatively strong recovery in sales over the near-term. This monthly indicator bears continued watching over the coming months in order to monitor the trend of this indicator in order to verify that the present very strong uptick is highly suggestive that a “turning point” in the industry’s near term sales is real and will be sustained. However, the model’s predicted sales forecast estimate for next month (May 2009) is projected to be $14.686 billion which would represent a yr-o-yr monthly sales growth of minus 27.5 percent – not very encouraging relative to sustainability of a sales improvement trend if the model’s May09 sales forecast estimate is born out. Time will tell ==> stay tuned for next month’s update.

About The Author

Mike Cowan, the developer of the Cowan LRA Model, is a 45-year semiconductor industry veteran. He has a 36-year history at IBM’s Microelectronics Division in East Fishkill, N.Y., where he was involved in many facets of semiconductor development and manufacturing engineering, including both technical and management responsibilities. Over his last ten years at IBM, as a senior technical staff member, he was involved in strategy development and competitive analysis focused on the semiconductor industry, and has developed a number of top-down and bottom-up models to predict the dynamics of the semiconductor industry. After retiring from IBM in 2002 he became an independent semiconductor industry analyst providing his monthly forecasts to The Semiconductor Reporter website from 2002 to 2006 and to Future Horizons during 2007 and 2008.

Cowan earned both BS and MS degrees in physics at Wayne State University in Michigan, and an MS in electrical engineering at Syracuse University in New York.

For more information regarding the model or the results, please contact Mike directly at: mikedcowan(at)verizon.net.

Toshiba's LaAlO3/SrGeX/Ge p-MISFET Gate Stack

I mentioned elsewhere that Intel’s approach of removing the oxide interlayer prior to high-K dielectric deposition was a significant advance on the road to scaling HKMG processes for the 16nm node.  This  joint effort with Sematech and UT Dallas will be presented at VLSI Technology Symposium 2009. Intel’s oxide-less gate stack technique might be signaling the direction they will be taking for future high-K processing which has a big impact on the rest of the logic manufacturers.

Although I overlooked the non-silicon channel transistor presentations at VLSI 2009, they are certainly a serious contender for future generations like 16nm. Intel themselves spend a great deal of effort seeking a silicon channel replacement. Many of my trusted colleagues believe that a new material will displace silicon for the transistor channel thereby extending the scalability of planar complimentary logic and avoiding the use of multiple gated, vertical channel transistors such as the FinFET. Of course, it’s a dangerous game to point to one Intel paper about technology that’s three nodes down Sheriff Moore’s road when Intel always explores as many technology options as possible before deciding on a direction for future production.

Intel has been busy pursuing possible replacements for silicon as the channel material for transistors., but they certainly aren’t the only ones as Toshiba’s presentation Monday afternoon in Kyoto proves.

In Session 4B devoted to the germanium MOSFET, Toshiba will present “New Approach to Form EOT-Scalable Gate Stack with Strontium Germanide Interlayer for High-k/Ge MISFETs.” The Toshiba paper claims the highest ever hole mobility in a p-channel FET with a peak value quoted of 481cm2/Vs. With only the abstract and the TEM image provided in the Toshiba release, it’s difficult to say how close they are to providing a viable solution for the equivalent oxide thickness (EOT) target of 0.5nm for the 16nm logic generation. The press release reports the cost of the strontium germanide interlayer is to increase the EOT by “only 0.2nm at the most.” It appears that the gate stack reported by Toshiba achieves a total EOT of “as thin as around 1nm.”

Toshiba has clearly done some great work in this area. They have also clearly demonstrated the LaAlO3/SrGeX/Ge p-MISFET as a technology option. But there are many hurdles standing between this work and getting this gate stack ready for the 16nm node. There appears to be less standing in the way of the Intel zero SiOx interface stack which claims an EOT of 0.59nm. That Intel-Sematech-UT Dallas paper will be presented in the Advanced Gate Stacks Session (3A) just a couple of hours before Toshiba.

One thing I really like about this paper is its return to the term MISFET which was sadly replaced long ago by the now familiar MOSFET.  For the PR professional, it’s all too close to misfit, of course, but in this new age of non-oxide gate dielectrics and even non-silicon channel materials, a more generic term is needed. Oddly, even the session title for Toshiba’s paper is “Ge MOSFET,” but as their abstract says, the strontium-germanide interlayer avoids the low-K oxides of germanium for the gate dielectric in their germanium channel devices. Still, I hope that even if an oxide ends up in the mix for whatever direction the industry widely adopts, we can keep MISFET because geeks – especially semicon geeks – like to think of themselves at least a little bit like misfits.

REvangelist at the ITC

It was interesting to be in Washington, DC, capitol of the free world and the free market economy on the very day that icon of American industry, General Motors, filed for bankruptcy. I was in Washington not to visit the Obama’s (alas they were out of town) but to testify at the US International Trade Commission (ITC) which is dedicated to making sure imports to the US market are handled fairly. As more companies get bought by the government, I wonder if this court’s power will grow along with taxpayer ownership of business. (By the way, if you’re thinking this sort of thing should be confidential, I was really only at the ITC to act as an evangelist for reverse engineering. My testimony was public.)

So why was being in Washington on the day GM filed for bankruptcy interesting? A better question might be how it relates to semiconductors, but I’ll try to get to that a bit later. On one of my many random walks around the capitol, I noticed a proliferation of big SUV’s in dark shades – mostly black. From what I saw, they are all Chevy Suburbans. Lying in wait at the back of the Capitol they sat quietly ready to move Secret Service against any potential threat from an unruly school tour group.

So my take on the governments’ (Yes, there were two. We tossed a few billion into GM Canada north of the border.), bailout plan is they wouldn’t know what to do without those big, black Suburbans. Maybe the Secret Service would have to resort to roof racks on their Ford Police Interceptors if the Suburban went out of production.

The New Chevrolet – for Government Use Only

I’ve worked with some people who once thought of the automotive electronics sector as a stabilizing force for the semiconductor industry because of the slow and steady growth it showed for many years. Lacking the dramatic crashes that often followed a big boom, automotive was considered “hot” in a certain way – at least if risk wasn’t your strong suit. I wonder what those same people are thinking now with our daily dose of news about plant closures, consolidation, and ultimately bailouts and bankruptcy. IC content in each new vehicle has been growing in leaps and bounds and analysts predict the electronics share of the value pie in future cars to reach 30% or more. But even this could be in doubt if cars like the Tata Nano catch on outside their launch market. It might be all we need, and it might be all we can afford in this failing economy.

Once more it seems, procrastination paid off and I’m happy that I didn’t spend more time thinking about automotive electronics. With the US in an economic depression and other big car markets hurting just as much, automotive electronics suppliers are getting hit pretty hard. But for the overall semiconductor market, it will have a very small effect. That makes me wonder about government bailouts, and what we could expect for our own industry.

Even with a President who strode BlackBerry in hand into the Whitehouse , could we really expect a bailout for a big semico? Maybe for RIM itself, the maker of the ubiquitous BB, it’s conceivable. I wonder if the machinery of government in our own little capital let alone big brother’s to the South could even run without BlackBerrys. Probably not.

But what of the chipmakers themselves? Surely there are iconic ones that would rival the image of GM in terms of 21st century American industrial might if people really took the time to consider it.

You would think with that little “Intel Inside” label in the lion’s share of PC’s inside the walls of Capitol Hill, the US chip industry would be front and center in discussions of ensuring US industrial power continues after the world gets through this financial crisis. But that’s probably giving too much credit. (Hey, isn’t that what started this whole mess?) Power comes to those who get elected, and the most politically active and vocal constituents that can march you into Ottawa or Washington are keeping attention focused on 19th century industries.

Fortunately, I doubt we will ever have to second guess our leaders for not bailing out Intel. Unlike the financial and automotive industries, Intel is a solid, well run business. In fact, Intel suffers the not quite so sweet end of government power as they are investigated and penalized for their relative strength compared to the competition.

For us in Canada, we suffered the complete meltdown of our jewel of hi-tech industry. Since the internet bubble burst, Nortel has been spiralling rapidly downward. Literally thousands of jobs disappeared – mostly right here in our nation’s capital yet our government paid little attention. On the other hand, the suggestion that a truck plant might close with the loss of a hundred jobs gets a reaction. It doesn’t take long to arrange a press conference timed for pick-up on the evening news to announce government commitment of a few hundred million to keep those jobs “here at home.”

But I think a bailout of a US-based semiconductor company is still a possibility, if they need it. With governments solidly in handout mode for business, the concept of need can be debated considering how many financial institutions grabbed money but now plan to give it back because they don’t want their business “hindered” by rules limiting executive bonuses. Maybe I should say, “If they ask for it.” I can see the Obama administration taking the view of IBM as a strategic entity for the country. Image is everything, especially in the age of the internet President, and Big Blue is certainly an icon of American industry even though it doesn’t build our PC’s or the chips inside them anymore. That’s not to say they aren’t building some of the stuff riding around in those black Suburbans on Capitol Hill though.

Last week I attempted to preview the upcoming VLSI Symposia. The conferences are in Japan this year, and my attention was quickly diverted to the current situation in the Japanese semiconductor industry. With all that off my chest, I am free this week to actually look at some of the papers that will be presented starting June 15 in Kyoto.

Maybe it’s because our industry and the whole economy is in the dumps and consolidation is on everyone’s mind or maybe I just didn’t pay much attention before. Either way, looking through the advance program’s list of authors, I was struck by what I thought were some unlikely collaborators.

Of course, there are the teams of researchers that you expect from the well known business partnerships. There is a joint AMD/IBM paper in the Special Technology Highlights Session on Tuesday. T7-2 is devoted to high-K, metal gate integration for 22nm “and beyond.” The full title gives a nice bump to the word count for this blog:

“Extremely Scaled Gate-First High-k/Metal Gate Stack with EOT of 0.55 nm Using Novel Interfacial Layer Scavenging Techniques for 22nm Technology Node and Beyond”

(I’m hoping these extra words count toward the practice I need to hit whatever the magic number is for writing that’s equivalent to the 10,000 hour principle described by Gladwell in Outliers.)

On the heels of this presentation is another collaborative work from AMD/IBM this time with the addition of Freescale. The title of T7-3 is more compact, but the long list of authors could really help if I was getting paid by the word. (Okay, I know what you’re thinking. If I’m getting paid for this, more than just blog readers are getting ripped off.) If all the contributors attend the session, there might not be room for you, but if not, it’s worth checking out.

The most interesting group of authors from AMD, IBM (TJ Watson Research), and Intel presenting research on a replacement technology for CMOS. It’s pretty academic and includes UCLA and University of Notre Dame participants, but it’s interesting that it’s not a Sematech activity which is where such an unlikely group of allies might be more expected. You could say it was just odd timing to discover this one since it was about the first time I read AMD and Intel in the same sentence after hearing about the EU ruling against Intel that may carry a fine of up to $1.4B if actually imposed. The EU’s fine was, after all, the result of some intense lobbying by AMD to governments in many regions to pay attention to what they claimed were monopolistic business practices. When they get together now, I wonder if these guys talk more about replacements for CMOS or what other jurisdictions might jump on the bandwagon against Intel now that the EU has taken the lead. For my part, I just wonder what happens to that money after it’s collected. Somehow, I doubt it will be used to drive innovation at AMD or anywhere else in order to improve the competitive landscape. I’m sure it will stimulate the economy though, at least for the restaurant industry (or wherever these bureaucrats rack up their expense accounts).

Getting away from politics for a second, the AMD-IBM-Intel paper is part of a special session 6B – “Beyond CMOS.” You could argue that such a session is hardly very special anymore since there have been so many. The larger question is the reason why so many of these panels, conference tracks, events, articles and webinars exist. Is it because judgement day for CMOS is really drawing near? Or is it just good marketing to leverage the fears of an industry with so much capital, manpower and training invested in CMOS technology?

Another presentation that caught my attention (and I wish I could attend) will be given by Samsung. My semiconductor analyst cronies and I have been wondering aloud how much scaling is left in Samsung’s landmark Spherical Recessed Array Transistor (S-RCAT) for DRAM. A change is expected soon since the S-RCAT appears to be approaching the limit at 56nm. Although technologists were impressed by this innovation from Samsung, the name RCAT was not all that exciting. Samsung PR folks are getting set to change that as they seem to be taking a more active role in naming their next technology. Samsung’s newest vertical DRAM cell transistor is going to be known as the TCAT – or Terabit Cell Array Transistor. “Terabit” is impressive sounding both in and outside technical circles. We live in a green age where the term climate change gave way to global warming which has recently been replaced by yet a newer brand name, perhaps tera or terra will manage to grab even more of the spotlight. And I shouldn’t leave out Canadian Football fans in Hamilton, Ontario. Samsung’s new DRAM transistor is bound to play well in TiCat country. (That last bit is included just for Steve Bitton, Industrial Control Design Lines editor at TechOnline and Hamilton TigerCat fanatic.)

In a related story (okay, I admit, that’s stretching things), CEA/LETI and STMicroelectronics will present a paper entitled, “GeOI and SOI 3D Monolithic Cell Integrations for High Density Applications.” If insulating substrates keep going (many don’t believe so) and germanium is adopted for the transistor channels (lots of important people believe this), then there is bound to be confusion down the road between “GeOI” chips and some future “GeoEye” satellite that is meant to track all of our movements. What if they need GeOI chips for the GeoEye satellite? That might be one FoxNews report worth watching.

For each of the jewels in the technology triple crown of conferences – IEDM, ISSCC, and VLSI – I hope to preview (and occasionally post-analyze) the papers. But what started as a quick look at the 2009 edition of the VLSI Circuits and Technology Symposia quickly veered into a commentary on the Japanese electronics industry.

This year, the conference site for the VLSI Circuits Symposium and the Technology Symposium is Kyoto, Japan. With the economy the way it is, we can expect a distinctly local flavor to these two events. The recession is the time to expect consolidation with some big mergers or acquisitions likely imminent. Semiconductor process development is getting so costly that it is definitely not for the faint of heart. (Is it only real men who own fabs?) Of course, partnerships are nothing new. The IBM fab club has been around for a long time through the Common Platform partnership. There is even some pre-competitive research going on through various entities like Sematech here in North America and SELETE in Japan. But I think things are moving beyond that. The most interesting news related to this was the Intel-TSMC announcement where Intel plans to move production of the mobile Atom processor to TSMC and eventually offer it as an IP core on the TSMC platform.

But Japan could be facing even bigger problems than what we see in North America or even Europe. It’s become casual to attach “unprecedented” to many things in the news, but round after round of big layoffs at several Japanese electronics giants is certainly that. Toshiba was one of the latest announcing 3,900 additional jobs eliminated adding to an earlier round where they shed 4,500 temporary workers. I’m not sure what Toshiba refers to as a temporary job, but perhaps it’s actually the term permanent position that needs more clarification these days. In any case, these measures appear quite drastic for conservative Japanese companies. Hopefully,  they have acted early enough and that nothing truly catastrophic faces the Japanese electronics industry.

Consolidation in Japan needs to happen now. NEC and Renesas appear set to merge. There is a possibility this will extend to include Panasonic as well since they were already engaged in some technology development with Renesas. Semiconductor Insights analysts have been deeply engaged for some time in preparing roadmaps to provide our technology outlook for the major players in the industry. The roadmap for Japanese semiconductor firms made me wonder how much technology development let alone IC volume manufacturing is in Japan’s future. All the big players appeared to be pushing hard into technology consortia like the IBM fab club or even partnering with TSMC like Fujitsu. Panasonic may be the last fab standing – at least for CMOS logic devices. If you think about it, that’s probably where Panasonic ranks considering they were the first manufacturer with a 45nm product on the market, beating even Intel.

Japan needs to continue to look beyond its borders and create global partnerships. Elpida is one company that has shown leadership in this area. To stay competitive with Samsung, Elpida moved to Taiwan through its partnership with Powerchip Semiconductor (PSC) back in 2003. If you want experience and expertise in huge volume manufacturing, Taiwan was and is the place to go. It was the only way to stay cost-competitive, and Elpida’s leadership realized that. Granted, a memory company needs to get that message earlier than a logic manufacturer given the commodity nature of memory, especially DRAM. Elpida continues to work hard on its manufacturing base in Taiwan with a 52% stake in Rexchip which seems to be the best positioned of the Taiwanese DRAM entities since the government’s plan to create the Taiwan Memory Corporation appears to be unravelling.

If 2003 was the year for a Japanese DRAM company to get into Taiwan, then 2009 may well be the year for a logic manufacturer to do the same. Right now, Fujitsu is considering its future on Formosa with TSMC. If they continue down that path, Fujitsu will be a survivor just like Elpida.

Nintendo DSi

I have to say I like the Nintendo DS. The popular gaming platform is a clever mix of form, function and fashion not to mention my initials. I wonder if Nintendo was thinking of me…Getting back to reality for a second (at least my version), the DS is worthy of more than my monogram…certainly the 100M unit sales mark that it recently surpassed. Although it was released last year in Japan, Nintendo appeared to time its launch of an upgraded version of the DS in North America dubbed DSi to coincide with the 100M sales mark.

Nintendo has been going for a different crowd along with the grade schoolers like my daughter. A cooking title was available for the DS, and as much as we might hope this was designed to get all those teens out there preparing meals for the whole family, Nintendo was obviously looking to expand its market to include young adults and perhaps even the parents who are shelling out for the consoles and games. You bought one for your kid, why be left out of the fun? Nintendo appears to be pushing the DSi with the young adult demographic, and this is evident on the “meet the DSi” site where you see college kids using it at a party in a high-tech game of “telephone.”

Since I haven’t enlisted any help from any part of the under 40 crowd, this post is not going to be very deep on game review. We need to get to the teardown and the chips inside the DSi.

Semiconductor Insights has torn both the Japanese and North American versions of the DSi. Here’s a quick run down of the devices that were uncovered:

Nintendo CPU (ARM9 + ARM11)

NEC 128Mbit 1T SRAM (North American Model)

Fujitsu 128Mbit FCRAM (Japanese Model)

Samsung moviNAND (2Gbit NAND + Controller die)

Atheros AR6002G Dual Band WiFi (2.4GHz + 5GHz)

Mitsumi MM3218 Single Band WiFi (2.4GHz)

ST Micro (Numonyx) Serial Flash (Code Storage)

Micron (Aptina) CMOS Image Sensor (VGA resolution)

The DSi sports two VGA camera modules. That will boost Aptina’s unit volumes in the months and years ahead, but will do little to showcase their image quality achievements. The DSi camera applications are clearly targeted to the youngest consumers. 640 by 480 images likely to get printed and sent to Grandma. The camera application is made for play – with distortion and some other cheesy effects most enjoyed by the pre-teen crowd. In fact the resolution and the type of “stamping” and graffiti effects mimic what’s inside my four-year-old’s toy V-tech camera.

I measured the imaging array size and calculated that the Aptina VGA sensor was built on a 2.2 micron pixel pitch technology – at least a generation behind the leading edge in production. This was confirmed after delayering the device and imaging in the SEM. It also revealed a pixel design and arrangement not previously seen in any Aptina or Micron Imaging device. I hope to dig up some more information about the new pixel for a future post. Stay tuned.

As I mentioned last week, there’s a lot of discussion about half nodes and “weak” nodes for logic technology. There’s no disputing that the semiconductor business ebbs and flows in predictable cycles, so there are points in time where the business climate may just not support gearing up for high volume production. If a downturn coincides with 45nm, then a foundry might want to refer to it as a “weak” node. You could argue that “weak” is more marketing spin than technical description. What makes 45nm less powerful than any other node? Considering Intel 45nm broke onto the scene with metal gates and high-K dielectrics, you might even say that 45nm was really pretty strong.

A more likely explanation is that investor confidence is a bit of an oxymoron these days, so corporate PR needs to avoid any suggestion that there is not enough business to recoup the investment in technology development for a major stop on the Gordon Moore highway. That’s at least part of what is at play at IBM, but its Semiconductor Research and Development Center VP, Gary Patton, was surprisingly forthcoming with Mark LaPedus at EETimes. According to LaPedus’ report, weak economic conditions coupled with leakage issues have refocused IBM onto 32nm. Mid nodes or half nodes are mentioned in Mark’s article in a new way that suggests their increased importance. He suggested that foundry customers would migrate straight to the “32/28nm” and skip the “45/40nm” node.

TSMC may not have been the first at 45nm, but they were the first foundry to the 40nm half node. They are set to do the same according to Electronics Weekly. As David Manners reported from the Globalpress Summit a few weeks ago, Altera asked TSMC for their most aggressive process. For logic, you could easily argue that the roadmap for logic processes belongs to Intel since it enacted the law that its co-founder proposed. Now, it seems that maybe TSMC is trying to draft their own legislation about the introduction of new process technologies.

A second piece in Electronics Weekly described the success of Altera’s FPGA product line. I’ll leave it to others to consider the chicken-and-egg story of the Stratix IV and the TSMC 40nm process that it’s built on. It appears that Altera has the 3G cellular deployment in China to thank. this may turn out to be a great success story for the FPGA versus custom ASIC’s. Maybe it’s even an uplifting bit of business news to think that the Chinese market is so hungry for new phones that the base station manufacturers just can’t wait for new chip designs to supply the demand.

Of course, we are all wondering, “When will this new technology actually hit the street?” As reported by Ron Wilson at EDN, Toppan Executive VP of sales and marketing Mike Hadsell suggests that “there may be significant 28 nm activity by early 2010.” If that’s the case, there may be very little lag between the launch of Intel’s 32nm process later this year and TSMC fabbed chips at 28nm.

Digging deeper into the news archives, Mark LaPedus talked about IBM’s view of the plans for 28nm at TSMC back in September, 2008. At the time, the announcement that they were delaying the roll out of a high-K metal gate process was viewed as “risky” for TSMC becuase it put them “behind” their competitors from Chartered, IBM and Samsung. Now it seems that their focus has been on 28nm all along. TSMC will not directly challenge Intel for the lead in technology, but it sure looks like they will be sticking to the bleeding edge.

TSMC recently launched their 40nm process technology. The first devices to roll out of Hsinchu were Altera’s Stratix IV FPGA’s. Semiconductor Insights process analysis team was the first to dig into TSMC’s newest offering.

TSMC’s 40nm process is a big milestone. They are the first foundry besides IBM to use embedded SiGe source/drains. The eSiGe provides compressive strain in the PFET channel to improve hole mobility which in turn increases current drive for the transistor. This TSMC technology milestone is arguably the most interesting discovery of the SI analysis team according to its author and Senior Process Analyst, Xu Chang. The shape of the SiGe source/drain regions is very distinctive in the TSMC 40nm device. Xu and his analysis colleagues have looked at every generation of both Intel and AMD/IBM eSiGe. The TSMC processing is very different than any other device to hit the market.

Unfortunately, that’s about all I can say about the TSMC device if I expect to keep my job. As much as they love SemiSerious, my bosses aren’t interested in supplying free reverse engineering data to increase readership. If you want to learn more, you need to buy the full report.

Moving a little past the “full” node of 45nm is a trend that seems to be developing – in two ways. First,  intermediate nodes are appearing. Some are almost skipping 45nm altogether with very little production planned. Of course, I’m talking about the IBM Common Platform who referred to 45nm as a “weak node.” They have focused all their energy onto 32nm As part of their announcements about their 32nm technology, IBM is talking about how easy it will be for customers to move from 32nm to 28nm.

I should also note that we did not detect any kill switches or other “rogue additions” as described in IEEE last year. That article is definitely worth reading even though it’s almost a year old. (I know. It’s inconceivable in the Twitter age.) I jumped on the link there because of Spectrum Online’s coverage of chips designed to thwart reverse engineers like me. That topic appears to be heating up because of the discovery of latent malware on some computers controlling several electrical utility operations in the US. With renewable energy adoption needing our power grid to get smarter, the use of typical mass market PC’s with cheap, off-the-shelf components was probably the one area Obama was counting on saving a few bucks of stimulus money. So were his new CTO, Aneesh Chopra, and CIO, Vivek Kundra. Imagine if someone suddenly decided to standardize on secure, military-grade microprocessors for every computer connected to the US power grid? Photovoltaic panel sales would no longer be dependent subsidies. We would all be paying so much to the power company for our electricity that a few thousand bucks for solar panels and batteries might seem pretty cheap.

In the TechInsights tradition, every attempt is made to inspire those designers, engineers and builders who actually do the work of creating technology. To highlight this, a special awards ceremony was held recently in San Francisco. As many of you know, Semiconductor Insights has offered leading technology companies a chance to showcase their best efforts through the Insights Awards which have been handed out to deserving products for many years. As part of the larger TechInsights family, the SI Insight Awards are now presented along with the EETimes ACE Awards at the Embedded Systems Conference (ESC) organized by the TechInsights events team.

The Insight Awards is a year-long process whereby companies who feel their chips are worthy of recognition provide them to the Semiconductor Insights’ crack technology analysis team. After analyzing the performance, circuit architecture and manufacturing processes of the nominees, several sessions are held where the lead analysts present the case for the finalists in each category. The result of the intense analytical scrutiny and many heated debates is our list of winners for this year.

The Insight Award for Most Innovative DRAM technology was given to Micron for their 50nm 1Gb DDR2. If you want to learn more about this most advanced RAM, the best place to start is a great Carl Wintgens article on EETimes.

In a world dominated by iPods and portable media, the award for Most Innovative Non-Volatile Memory obviously holds special distinction (as well as well as contributing extra heat to the winners debates). This year’s very worthy recipient is Toshiba for their 43nm 16Gb NAND flash.

The third device category award in 2009 was presented for the Most Innovative Mobile Processor. The winner was Intel for the Atom processor. Who can argue? Intel devices power the lion’s share of netbooks, the hottest computing platform currently on the market. Not only that, but Intel is leading this charge with the most advanced logic process available today – its 45nm High-K metal gate technology.

And finally the award closest to my heart, for Most Innnovative Process Technology, went to IMFT for its 34nm, 32Gbit MLC, NAND Flash. Since this is an Intel-Micron JV, the Process Technology Award made it two each for both Intel and Micron. As SI’s GM, Emil Alexov pointed out at the ceremony, this is the first product beyond 40nm that we have analyzed. That’s quite a milestone, and it’s no surprise that it is was achieved through the collaboration of the likes of Intel and Micron.

For more a great roundup of ESC and the EETimes ACE Awards and the gala evening, your best bet is to go to see Junko Yoshida’s article on EETimes. The full list of winners is here and the photo gallery of the presentations is also available. The ACE presentations at ESC 09 included some special IEEE ACE honors as well. Please go to the excellent Spectrum Tech Talk blog to get their angle on the event.

So if you won for 2009, there’s no time to lose. Contact the awards coordinator (cystalc@semiconductor.com) to submit your best for 2010. If you didn’t win, our analysis team certainly did not minimize your accomplishments. There were many worthy finalists. Picking the winner was nothing close to easy. (If you read a previous post, you may have heard that it was a “long and sometimes arduous” process.) But if seeing your least favorite competitor receiving the championship trophy left a bad taste in your mouth, what better time is there to let us know why you deserve the crown in 2010?

Informally (which is certainly not to suggest that anything that goes on SemiSerious is formal) I keep a list of acronyms which are used for different things in different fields. With my memory being what it is, very few of these make it out of the dark recesses of my mind and into the light of day. That said, though, there is a danger of the topic turning into a serial item for this blog. (I know. Aren’t we all desperate for content.) Re-use of acronyms can get interesting and confusing when not too distant fields, let’s say two within the semiconductor industry itself, use the same TLA to refer to completely different things.

As I mentioned in a recent post, Semiconductor Insights technology analysts along with our Portelligent and EETimes colleagues have begun the task of selecting the winners for our annual Insight Awards recognizing the most innovative technologies appearing in the last year. A new award category for this year is the Mobile Processor. Without giving too much away regarding who may win the award for Most Innovative Mobile Processor, our analyst discussion turned to the netbook and the emerging category of device known as “MID” or mobile internet device as Wikipedia will inform you.

In fact, the top item returned from Google is this form of MID which takes you directly to the Wikipedia entry. There is actually a site for MID – mid.org, but that’s really not where I was headed with this post (that seemed like a good idea when working late and trying to avoid getting anything productive done.) The late night and what has piqued my interest lately is the history of solid-state imaging. And that’s where the other MID comes in. Image sensor techies who have been around long enough will know what I’m talking about. Long before CMOS image sensors were popular enough to be known as “CIS,” there were references to “MOS Imaging Devices.”

Okay, maybe these two MID’s are too far distant in time if not in technical field, but I think that’s what made it seems worth a blog post (right – it doesn’t take much). On the same day when I had the chance to participate in identifying one point on technology’s cutting edge, I was also digging progressively further back into history. And those two activities both brought me to MID.